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參數(shù)資料
| 型號： | UPD75068CU |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 19/68頁 |
| 文件大小： | 640K |
| 代理商： | UPD75068CU |
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19
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Subsystem
clock generator
Main system
clock generator
Watch timer
Basic interval timer (BT)
Timer/event counter
Serial interface
Watch timer
A/D converter
(successive approximation type)
INT0 noise eliminator
Clock output circuit
1/2 to 1/4096
Frequency divider
Selec-
tor
Selec-
tor
Frequency
divider
CPU
INT0 noise
eliminator
Clock output
circuit
Φ
Oscillator
disable
signal
I
HALT
Note
STOP
Note
PCC2, PCC3
clear signal
Wait release signal from BT
Standby release signal from
interrupt control circuit
RESET signal
XT1
XT2
X1
X2
4
WM.3
SCC
SCC3
SCC0
PCC
PCC0
PCC1
PCC2
PCC3
STOP F/F
Q
S
R
HALT F/F
S
Q
R
f
XT
f
X
1/21/16
1/4
5.2 Clock Generator
The clock generator operates according to the statuses of the processor clock control register (PCC) and
the system clock control register (SCC). Two types of clock are provided: main system clock and subsystem
clock, and the instruction execution time can be changed.
0.95
μ
s / 1.91
μ
s / 15.3
μ
s (operated with main system clock at 4.19 MHz)
122
μ
s (operated with subsystem clock at 32.768 kHz)
Figure 5-1. Clock Generator Block Diagram
Note
Instruction execution
Remarks
1.
f
X
= Main system clock frequency
2.
f
XT
= Subsystem clock frequency
3.
4.
PCC: Processor clock control register
5.
SCC: System clock control register
6.
One clock cycle (t
CY
) at
Φ
is equal to one machine cycle of an instruction.
For t
CY
, refer to
AC Characteristics in 10. ELECTRICAL SPECIFICATIONS
.
Φ
= CPU clock
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