11
μ
PD75112(A), 75116(A)
4. Memory Configuration
Program Memory (ROM)
12160
×
8 bits (0000H to 2F7FH):
μ
PD75112(A)
16256
×
8 bits (0000H to 3F7FH):
μ
PD75116(A)
0000H to 0001H: Vector table for writing the
program start address by reset
0002H to 000BH: Vector table for writing the
program start address by interrupt
Remarks
: In all other cases, the program can be
branched by the BR PCDE and BR PCXA
0020H to 007FH: Table area to be referred to
by the GETI instruction
Data Memory
Data area
512
×
4 bits (000H to 1FFH)
Peripheral hardware area
128
×
4 bits (F80H to FFFH)
instructions to an address with only the
lower 8 bits of PC changed.
Figure 4-1 Program Memory Map (
μ
PD75112(A))
Address
≈
≈
≈
MBE RBE
MBE RBE
MBE
MBE RBE
MBE RBE
MBE RBE
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
7
6
0
Internal Reset Start Address
Internal Reset Start Address (Low-Order 8 Bits)
INTBT/INT4 Start Address (High-Order 6 Bits)
INT0/INT1 Start Address (High-Order 6 Bits)
RBE
INT0/INT1 Start Address
(Low-Order 8 Bits)
(Low-Order 8 Bits)
INTSIO Start Address (High-Order 6 Bits)
INTSIO Start Address
(Low-Order 8 Bits)
INTT0 Start Address (High-Order 6 Bits)
INTT0 Start Address
(Low-Order 8 Bits)
INTT1 Start Address (High-Order 6 Bits)
INTT1 Start Address
GETI Instruction Reference Table
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
BR !addr
Instruction
Branch
Address
CALL !addr
Instruction
Subroutin
Entry
Address
BRCB !caddr Instruction
Branch Address
≈
(High-Order 6 Bits)
INTBT/INT4 Start Address
(Low-Order 8 Bits)
≈
≈
≈
≈
≈
≈
2000H
1FFFH
2F7FH
BRCB !caddr Instruction
Branch Address
BR $addr
Instruction
Relative
Branch Address
(-15 to +16)
Branch Address
Subroutine Entry
Address by GETI
Instruction