12
μ
PD75208
4.
ARCHITECTURE AND MEMORY MAP OF THE
μ
PD75208
The
μ
PD75208 has three architectural features:
Bank configuration of data memory
: Static RAM (448 words
×
4 bits)
Display data memory (49 words
×
4 bits)
Peripheral hardware (128
×
4 bits)
Bank configuration of general registers: 8
×
4 banks (for operation in 4-bit units)
4
×
4 banks (for operation in 8-bit units)
Memory mapped I/O
Fig. 4-1 and 4-2 show the memory maps for the
μ
PD75208.
Fig. 4-1 Program Memory Map
Remarks
In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC
changed is enabled by BR PCDE and BR PCXA instructions.
MBE RBE
0
7
6
5
0000H
Address
MBE RBE
0
0002H
MBE RBE
0
0004H
MBE RBE
0
0006H
MBE RBE
0
0008H
MBE RBE
0
000AH
007FH
0080H
0020H
1F7FH
0
Internal Reset Start Address High-Order 5 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
INTBT/INT4 Start Address (High-Order 5 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
INT0 Start Address (High-Order 5 Bits)
INT0 Start Address (Low-Order 8 Bits)
INT1 Start Address (High-Order 5 Bits)
INT1 Start Address (Low-Order 8 Bits)
INTSIO Start Address (High-Order 5 Bits)
INTSIO Start Address (Low-Order 8 Bits)
INTT0 Start Address (High-Order 5 Bits)
INTT0 Start Address (Low-Order 8 Bits)
NTTPG Start Address (High-Order 5 Bits)
INTTPG Start Address (Low-Order 8 Bits)
INTKS Start Address
(High-Order 5 Bits)
INTKS Start Address
(Low-Order 8 Bits)
GETI Instruction Reference Table
000EH
MBE RBE
0
MBE RBE
0
000CH
07FFH
0800H
0FFFH
1000H
BRCB
! caddr Instruction
Branch Address
CALL ! addr
Instruction
Subroutine Entry
Address
BR ! addr
Instruction Branch
Address
BR $addr
Instruction
Relative Branch
Address
(–15 to –1,
+2 to +16)
BRCB
! caddr
Instruction
Branch
Address
CALLF
! faddr
Instruction
Entry
Address
Branch Destination
Address Specified
by GETI Instruction,
Subroutine Entry
Address