參數資料
型號: UPD75208
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機
文件頁數: 40/62頁
文件大?。?/td> 497K
代理商: UPD75208
40
μ
PD75208
V
DD
= Oscillation
voltage range
After V
DD
reaches the
minimum value in
the oscillation
voltage range
V
DD
= 4.5 to 6.0 V
Oscillator frequency
(f
XX
)
*2
Oscillation
stabilization time
*3
Oscillator frequency
(f
XX
)
*2
Oscillation stabilization
time
*3
X1 input frequency
(f
X
)
*2
X1 input high and low
level widths (t
XH
, t
XL
)
2.0
2.0
2.0
100
4.19
5.0
*4
4
5.0
*4
10
30
5.0
*4
250
MHz
ms
MHz
ms
ms
MHz
ns
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
PARAMETER
RECOMMENDED CIRCUIT
RESONATOR
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85
°
C, V
DD
= 2.7 to 6.0 V)
Oscillator frequency
(f
XT
)
*2
Oscillation stabilization
time
*3
XT1 input frequency
(f
XT
)
XT1 input high and low
level widths (t
XTH
, t
XTL
)
V
DD
= 4.5 to 6.0 V
32.768
1.0
35
2
10
100
32
kHz
s
s
kHz
μ
s
Ceramic
resonator
*1
Crystal
resonator
*1
External
clock
Crystal
resonator
*1
External
clock
32
32
10
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
PARAMETER
RECOMMENDED CIRCUIT
RESONATOR
X1
X2
C1
C2
X1
X2
C1
C2
X1
X2
PD74HCU04
μ
XT1
Leave Open
XT2
XT1
XT2
C3
C4
330 k
#
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85
°
C, V
DD
= 2.7 to 6.0 V)
*
1.
Resonators are shown in the following page.
2.
Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution
time.
3.
Time required for oscillation to become stabilized after V
DD
application or STOP mode release.
4.
When oscillator frequency is " 4.19 < f
X
5.0 MHz ", do not select " PCC = 0011 " as instruction execution time.
If " PCC = 0011 " is selected, 1 machine cycle becomes less than 0.95
μ
s, with the result that the specified MIN.
value of 0.95
μ
s cannot be observed.
*
1.
Recommended resonators are shown in the following page.
2.
Oscillator characteristics only. Refer to the description of AC characteristics for instruction execution time.
3.
Oscillation stabilization time is a time required for oscillation to become stabilized after V
DD
application or
STOP mode release.
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