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40
μ
PD75312B, 75316B
Operation
Skip Condition
Operand
Mne-
monic
Address-
ing Area
B
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
addr
!addr
$addr
!caddr
!addr
!faddr
rp
BS
rp
BS
IE
× × ×
IE
× × ×
CY
←
CY
∧
(fmem.bit)
V
CY
←
CY
∧
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
V
CY
←
CY
∧
(H + mem
3-0
.bit)
V
CY
←
CY
V
(fmem.bit)
CY
←
CY
V
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
CY
←
CY
V
(H + mem
3-0
.bit)
CY
←
CY
V
(fmem.bit)
CY
←
CY
V
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
CY
←
CY
V
(H + mem
3-0
.bit)
PC
13–0
←
addr
(The assembler selects the optimum instruction
from among the BR !addr, BRCB !caddr, and BR
$addr instructions.)
PC
13–0
←
addr
PC
13–0
←
addr
PC
13–0
←
PC
13, 12
+ caddr
11–0
(SP – 4) (SP – 1) (SP – 2)
←
PC
11–0
(SP – 3)
←
MBE, 0, PC
13
, PC
12
PC
13–0
←
addr, SP
←
SP – 4
(SP – 4) (SP – 1) (SP – 2)
←
PC
11–0
(SP – 3)
←
MBE, 0, PC
13
, PC
12
PC
13–0
←
00, faddr, SP
←
SP – 4
MBE, PC
13
, PC
12
←
(SP + 1)
3, 1, 0
PC
11–0
←
(SP) (SP + 3) (SP + 2)
SP
←
SP + 4
MBE, PC
13
, PC
12
←
(SP + 1)
3, 1, 0
PC
11–0
←
(SP) (SP + 3) (SP + 2)
SP
←
SP + 4, then skip unconditionally
PC
13
, PC
12
←
(SP + 1)
1, 0
PC
11–0
←
(SP) (SP + 3) (SP + 2)
PSW
←
(SP + 4) (SP + 5), SP
←
SP + 6
(SP – 1) (SP – 2)
←
rp, SP
←
SP – 2
(SP – 1)
←
MBS, (SP – 2)
←
0, SP
←
SP – 2
rp
←
(SP + 1) (SP), SP
←
SP + 2
MBS
←
(SP + 1), SP
←
SP + 2
IME
←
1
IE
× × × ←
1
IME
←
0
IE
× × × ←
0
2
2
2
2
2
2
2
2
2
—
3
1
2
3
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
3
2
2
3
2
3
3+S
3
1
2
1
2
2
2
2
2
*4
*5
*1
*4
*5
*1
*4
*5
*1
*6
*6
*7
*8
AND1
OR1
XOR1
BR
BRCB
CALL
CALLF
RET
RETS
RETI
PUSH
POP
EI
DI
Notes 1.
Instruction Group
2.
Interrupt control
M
C
Unconditional
*6
*9
N
B
S
N
M