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參數(shù)資料
| 型號： | UPD753208 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 4位單晶片微控制器 |
| 文件頁數(shù)： | 39/80頁 |
| 文件大?。?/td> | 577K |
| 代理商： | UPD753208 |
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39
μ
PD753204, 753206, 753208
Table 9-1. Status of Each Device After Reset (1/2)
Hardware
RESET signal generation
in the standby mode
RESET signal generation
during operation
Program counter (PC)
μ
PD753204
Sets the low-order 4 bits of
program memory’s address
0000H to PC11 to PC8 and
the contents of address 0001H
to PC7 to PC0.
Sets the low-order 4 bits of
program memory’s address
0000H to PC11 to PC8 and
the contents of address 0001H
to PC7 to PC0.
μ
PD753206,
μ
PD753208
Sets the low-order 5 bits of
program memory's address
0000H to PC12 to PC8 and
the contents of address 0001H
to PC7 to PC0.
Sets the low-order 5 bits of
program memory's address
0000H to PC12 to PC8 and
the contents of address 0001H
to PC7 to PC0.
PSW
Carry flag (CY)
Held
Undefined
Skip flag (SK0-SK2)
0
0
Interrupt status flag (IST0, IST1)
0
0
Bank enable flag (MBE, RBE)
Sets bit 6 of program memory’s
address 0000H to RBE and bit
7 to MBE.
Sets bit 6 of program memory’s
address 0000H to RBE and bit
7 to MBE.
Stack pointer (SP)
Undefined
Undefined
Stack bank select register (SBS)
1000B
1000B
Data memory (RAM)
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
0, 0
Basic interval
Counter (BT)
Undefined
Undefined
timer/watchdog
Mode register (BTM)
0
0
timer
Watchdog timer enable flag (WDTM)
0
0
Timer/event
Counter (T0)
0
0
counter (T0)
Modulo register (TMOD0)
FFH
FFH
Mode register (TM0)
0
0
TOE0, TOUT F/F
0, 0
0, 0
Timer
Counter (T1)
0
0
counter (T1)
Modulo register (TMOD1)
FFH
FFH
Mode register (TM1)
0
0
TOE1, TOUT F/F
0, 0
0, 0
Timer
Counter (T2)
0
0
counter (T2)
Modulo register (TMOD2)
FFH
FFH
High-level period setting modulo
register (TMOD2H)
FFH
FFH
Mode register (TM2)
0
0
TOE2, TOUT F/F
0, 0
0, 0
REMC, NRZ, NRZB
0, 0, 0
0, 0, 0
TGCE
0
0
Watch timer
Mode register (WM)
0
0
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