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10
μ
PD75336
Clocked
Asynchronous
Asynchronous
I/O Circuit
Type
*
B - C
E - E
E - B
E - B
E - B
F - A
F - B
M - C
B
B - C
B - C
F - A
F - A
––
––
B
––
––
––
3.2
NON-PORT PINS (1/2)
V
SS
Function
External event pulse input to timer/event counter
Timer/event counter output
Clock output
Fixed frequency output (for buzzer or system clock trim-
ming)
Serial clock input/output
Serial data output
Serial bus input/output
Serial data input
Serial bus input/output
Edge detection vectored interrupt input (both rising edge
and falling edge detection effective)
Edge detection testable input (ris-
ing edge detection)
Parallel falling edge detection testable input
Parallel falling edge detection testable input
Main system clock oscillation crystal/ceramic connection
pin. For external clock, the external clock signal is input to
X1 and its opposite phase is input to X2.
Subsystem clock oscillation crystal connection pin. For
external clock, the external clock signal is input to XT1 and
XT2 is opened. XT1 can be used as a 1-bit input (test).
System reset input
Internally Connected. Connect the IC pin to V
DD
directly.
Positive power supply
GND potential
Pin Name
TI0
TI1
PTO0
PTO1
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0 to KR3
KR4 to KR7
X1
X2
XT1
XT2
Dual-
Function Pin
P13
P80
P20
P21
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60 to P63
P70 to P73
—
—
—
—
—
—
Input/Output
Input
Output
Output
Output
Input/output
Input/output
Input/output
Input
Input
Input
Input
Input
Input
Input
––
Input
—
—
—
Reset
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
––
—
—
—
—
—
RESET
IC
V
DD
*
: Schmitt triggered input
Edge detection vectored interrupt
input (detection edge selectable)