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36
μ
PD75336
Table 8-1 Status after Reset of Each Hardware (1/2)
Hardware
Program counter (PC)
Carry flag (CY)
Skip flag (SK0 to SK2)
PSW
Interrupt status flag (IST0)
Bank enable flag (MBE, RBE)
Stack pointer (SP)
Data memory (RAM)
General register (X, A, H, L, D, E, B, C)
Bank selection register (MBS, RBS)
Counter (BT)
Mode register (BTM)
Counter (Tn)
Modulo register (TMODn)
Mode register (TMn)
TOEn, TOUT F/F
Mode register (WM)
Shift register (SIO)
Operating mode register (CSIM)
SBI control register (SBIC)
Slave address register (SVA)
Processor clock control register (PCC)
System clock control register (SCC)
Clock output mode register (CLOM)
Display mode register (LCDM)
Display control register (LCDC)
Mode register (ADM), EOC
SA register
Basic interval
timer
Timer/event
counter
(n = 0, 1)
Watch timer
Serial interface
Clock generator,
clock output
circuit
LCD controller
A/D converter
RESET Input in Standby
Mode
Low-order 6 bits of program
memory address 0000H are
set to PC13 to PC8 and the
contents of address 0001H
are set in PC7 to PC0.
Held
0
0
Bit 6 of program memory
address 0000H is set in RBE,
and bit 7 is set to MBE.
Undefined
Held
*
Held
0, 0
Undefined
0
0
FFH
0
0, 0
0
Held
0
0
Held
0
0
0
0
0
04H (EOC = 1)
7FH
Undefined
0
0
FFH
0
0, 0
0
Undefined
0
0
Undefined
0
0
0
0
0
04H (EOC = 1)
7FH
RESET Input during
Operation
Low-order 6 bits of program
memory address 0000H are
set to PC13 to PC8 and the
contents of address 0001H
are set in PC7 to PC0.
Undefined
0
0
Bit 6 of program memory
address 0000H is set in RBE,
and bit 7 is set to MBE.
Undefined
Undefined
Undefined
0, 0
*
Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.