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參數(shù)資料
| 型號(hào)： | UPD75402AGBA |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 34/48頁(yè) |
| 文件大?。?/td> | 515K |
| 代理商： | UPD75402AGBA |
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34
μ
PD75402A(A)
SBI mode (SCK ··· Internal clock output (master)):
SBI mode (SCK ··· External clock input (slave)):
Note
R
L
and C
L
are the resistance and capacitance of the SO output line load respectively.
Min.
1600
3800
t
KCY3
/2 – 50
t
KCY3
/2 – 150
150
t
KCY3
/2
0
0
t
KCY3
t
KCY3
t
KCY3
t
KCY3
Parameter
SCK cycle time
SCK high/low level
width
SB0 setup time
(referred to SCK
↑
)
SB0 hold time
(referred to SCK
↑
)
Delay from SCK
↓
to
SB0 output
Delay from SCK
↑
to SB0
↓
Delay from SB0
↓
to SCK
↓
SB0 low-level width
SB0 high-level width
Symbol
t
KCY4
t
KL4
t
KH4
t
SIK4
t
KSI4
t
KSO4
t
KSB
t
SBK
t
SBL
t
SBH
Symbol
t
KCY3
t
KL3
t
KH3
t
SIK3
t
KSI3
t
KSO3
t
KSB
t
SBK
t
SBL
t
SBH
Parameter
SCK cycle time
SCK high/low level
width
SB0 setup time
(referred to SCK
↑
)
SB0 hold time
(referred to SCK
↑
)
Delay from SCK
↓
to
SB0 output
Delay from SCK
↑
to SB0
↓
Delay from SB0
↓
to SCK
SB0 low-level width
SB0 high-level width
Typ.
Max.
250
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
Conditions
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
R
L
= 1 k
,
C
L
= 100 pF
Note
V
DD
= 4.5 to 6.0 V
Min.
800
3200
400
1600
100
t
KCY4
/2
0
0
t
KCY4
t
KCY4
t
KCY4
t
KCY4
Typ.
Max.
300
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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