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參數(shù)資料
| 型號： | UPD75402AGBA |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 515K |
| 代理商： | UPD75402AGBA |
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8
μ
PD75402A(A)
3.2 NON-PORT PINS
Remark
See Chapter 8 for each pin status during resetting.
Note
Connect the NC pin directly to the V
SS
pin when the
μ
PD75402A(A) shares the printed circuit board
with the
μ
PD75P402 in emulation.
3.3 PIN INPUT/OUTPUT CIRCUITS
The I/O circuits of the
μ
PD75402A(A) are roughly shown on the next and subsequent pages.
Table 1-1 I/O Circuit Type of Pin
Remark
The types in circles have a Schmitt-triggered input.
Pin
INT0
INT2
SI
SO
SCK
SB0
PCL
X1, X2
RESET
V
DD
V
SS
NC
Note
I/O
Input
Input
Input
I/O
I/O
I/O
I/O
Input
Input
–
–
–
Dual-
function pin
P10
P12
P03
P02/SB0
P01
P02/SO
P22
–
–
–
–
–
Function
Edge detection vectored interrupt request input pin (A detected edge
can be selected by the mode register.)
Connects with the built-in noise eliminator using a sampling clock.
Edge detection external test input pin (A rising edge is detected.)
Serial data input pin
Serial data output pin
Serial clock I/O pin
Serial bus I/O pin
Clock output pin
Pin for connection to a crystal/ceramic resonator for system clock
generation. An external clock is applied to X1, and its reverse phase to
X2.
System reset input pin, which connects with the built-in noise elimina-
tor using an analog delay.
Positive power supply pin
Ground potential pin
No connection
Pin
P00
P01/SCK
P02/SO/SB0
P03/SI
P10/INT0
P12/INT2
Pin
P20, P21, and P23
P22/PCL
P30 - P33
P50 - P53
P60 - P63
RESET
I/O type
E-B
E-B
M
E-B
I/O type
-A
-B
-C
-C
B
B
B
B
F
F
B
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