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參數(shù)資料
| 型號： | UPD765A |
| 廠商： | NEC Corp. |
| 英文描述： | Single/Double Density Floppy-Disk Controller |
| 中文描述： | 單/雙密度軟盤控制器 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 344K |
| 代理商： | UPD765A |
uPD765A/uPD765B
NEC
Pin Identific ation
No.
1
Symbol
RESET
RD
WR
CS
2
3
4
5
A0
DB0-DB7
DRQ
DACK
T C
INDEX
INT
C L K
G ND
W C L K
W IND O W
6-13
14
15
16
17
18
19
Function
Reset input
Read control input
Write control input
Chip select input
Data or status select input
Bidirectional data bus
DMA request output
DMA acknowledge input
Termnal count input
Index input
Interrupt request output
20
21
22
23
R
DATA
S Y NC
W E
MF M
SIDE
USn
US1
WDATA
24
25
26
27
28 29
Clock input
Ground
Write clock input
Read data window input
Read data input
VCO sync output
Write enable output
MFMoutput
Head select output
FDD unit select output
Write data output
Preshift
output
Fault/track zero input
Write protect/two side
input
Ready
input
Head load output
Fault reset/step output
Low current direction
output
Read/write/ seek output
DC power
(
+5
V)
30
31, 32
33
34
PS0
FLT/TRK0
WPRT/2SIDE
PS1
35
36
37
38
READY
H D L D
FLTR/STEP
LCT/DIR
39
40
m/SEEK
k c
Pin Func tions
RESET (Reset)
The RESET input places the FDC in the idle state. It re-
sets the output lines to the FDD to 0 (low), except PSO, 1
and WDATA (undefined), INT and DRQ also go low;
DBO-7 goes to an input state. It does not affect SRT,
HUT, or HLT in the Specify command. If the RDY input is
held high during reset, the FDC will generate an inter-
rupt within
1.024ms.
To clear this interrupt, use the
Sense Interrupt Status command.
INT (Interrupt)
The INT output is
FDC’s
interrupt request. In Non-DMA
mode, the signal is output for each byte. In DMA mode,
it is output at the termination of a command operation.
CLK (Clock)
CLK is the input for the
FDC’s
single-phase,
lTL-level
squarewave clock: 8 MHz or 4 MHz. (Requires a pull-up
resistor.)
RD (Read Strobe)
The RD input allows the transfer of data from the FDC
to the data bus when low and either
CS
or DACK is
asserted.
WR (Write Strobe)
TheWR
input allows the transfer of data to the FDC
from the data bus when low. Disabled when
CS
is high.
A0 (Data/Status
Select)
The
A0
input selects the data register
(A0
= 1) or status
register
(A0=O)
contents to be accessed through the
data bus.
CS
(Chip Select)
The FDC is selected when
CS
is low, enabling
RD
and
WR.
DBo-DB7 (Data Bus)
DBo-DB7
are a bidirectional
8-bit
data bus. Disabled
when
CS
is high.
DRQ (DMA Request)
The FDC asserts the
DRQ output
high to request a DMA
transfer.
DACK (DMA Acknowledge)
When the DACK input is low, a DMA cycle is active and
the controller is performing a DMA transfer.
TC (Terminal Count)
When
theTC
input is high, it indicates the termination of
a DMA transfer. It terminates data transfer during
Read/
Write/Scan commands in DMA or interrupt mode.
INDEX (Index)
The INDEX input goes high at the beginning of a disk
track.
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