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參數(shù)資料
| 型號(hào)： | UPD77015 |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16 bits, Fixed-point Digital Signal Processor |
| 中文描述： | 16位定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 43/60頁 |
| 文件大?。?/td> | 424K |
| 代理商： | UPD77015 |
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μ
PD77015, 77017, 77018
43
Serial Interface
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK input cycle time
t
cSC
2t
cC
ns
SCK input high/low level width
t
wSC
25
ns
SCK input rise/fall time
t
rfSC
20
ns
SOEN recovery time
t
recSOE
20
ns
SOEN hold time
t
hSOE
0
ns
SIEN recovery time
t
recSIE
20
ns
SIEN hold time
t
hSIE
0
ns
SI setup time
t
suSI
20
ns
SI hold time
t
hSI
0
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SORQ output delay time
t
dSOR
30
ns
SORQ hold time
t
hSOR
0
ns
SO valid time
t
vSO
30
ns
SO hold time
t
hSO
0
ns
SIAK output delay time
t
dSIA
30
ns
SIAK hold time
t
hSIA
0
ns
Notes for Serial Clock
Serial clock inputs SCK1 and SCK2 are sensitive to any kind of interfering signals (noise on power supply,
induced voltage, etc.). Spurious signals can cause malfunction of the device. Special care for the serial clock
design should be taken. Careful grounding, decoupling and short wiring of SCK1 and SCK2 are recommended.
Intersection of SCK1 and SCK2 with other serial interface lines or close wiring to lines carrying high frequency
signals or large changing currents should be avoided.
It considers for the serial clock to make a waveform stable especially about the rising and falling.
Example 1. good example
Straight rising form and falling
form
Example 2. no good example
It doesn’t bound. It doesn’t make
noise one above another.
Example 3. no good example
It doesn’t make a stair stepping.
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