參數(shù)資料
型號(hào)： UPD77015GC
廠商： NEC Corp.
元件分類： 數(shù)字信號(hào)處理
英文描述： 16 bits, Fixed-point Digital Signal Processor
中文描述： 16位定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 22/60頁(yè)
文件大?。?/td> 424K
代理商： UPD77015GC
μ
PD77015, 77017, 77018
22
2.4.3 Data Memory Addressing
There are following two types of data memory addressing.
Direct addressing
The address is specified in the instruction field.
Indirect addressing
The address is specified by the data pointer (DP). DP can get a bit reverse before addressing. It can
update the DP value after accessing data memory.
2.5 On-chip Peripheral Circuit
The
μ
PD77017 includes serial interface, host interface, general input/output ports and wait cycle registers.
They are mapped in both X and Y memory areas, and are accessed as memory mapped I/O by the
μ
PD77017
CPU.
2.5.1 Serial Interface Outline
The
μ
PD77017 has 2 channel serial interfaces. Serial I/O clock must be provided from external. Frame length
can be programmed independently to be 8 bits or 16 bits. MSB first or LSB first can also be selected. Data is
input/output by hand shaking for an external device, and by interrupts, polling or wait function in internal.
2.5.2 Host Interface Outline
The
μ
PD77017 has 8 bits parallel ports as host interface to input/output data to and from host CPU and DMA
controller. When an external device accesses host interface, HA0 and HA1 pins; which are host address input
pins; specifies bit 15 to bit 8 and bit 7 to bit 0. The
μ
PD77017 includes 3 registers consisting of 16 bits, which
are dedicated for input data, output data and status. The
μ
PD77017 has three types of interface method for
internal and external data; interrupts, polling and wait function.
2.5.3 General Input/output Ports Outline
General input/output ports consist of 4 bits. User can set each port as input or output. The
μ
PD77017 includes
two registers. One is 4 bits register for input/output data, and the other is 16 bits for control.
2.5.4 Wait Cycle Register
The wait cycle registers consist of 16 bits. It is used to set wait cycle number when external memory is
accessed. When external data memory area (C000H - FFFFH) is accessed, 0, 1, 3, or 7 wait cycle can be set.
When external data memory area is accessed, wait cycle can be also set by WAIT pin.
相關(guān)PDF資料
PDF描述
UPD77017 16 bits, Fixed-point Digital Signal Processor
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