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參數(shù)資料
| 型號(hào)： | UPD7759GC-3BH |
| 廠商： | NEC Corp. |
| 英文描述： | ADPCM SPEECH SYNTHESIZER LSIs |
| 中文描述： | 差分PcM語(yǔ)音合成器大規(guī)模集成電路 |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大?。?/td> | 183K |
| 代理商： | UPD7759GC-3BH |
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μ
PD7759
4
1.2 PIN FUNCTION FOR STAND ALONE MODE
Pin
(Abbre-
viation)
52-pin
QFP
Pin No.
40-pin
DIP
Pin No.
I/O
Function
I0
I1
I2
I3
I4
I5
I6
I7
11
12
15
16
17
18
19
21
4
5
6
7
8
9
Message selection code input.
The message selection code signals are positive logics.
Ground the pins not used.
These pins are connected to the internal latch circuit which
latches I0 to I7 data at the rising edge of the ST input.
In standby mode, these pins should be set high or low level.
If they are biased at or near the typical CMOS threshold,
the excess supply current is caused.
10
11
This signal is at low level while address signal is valid.
Controls the latch circuit for the higher 8 bits of the external
ROM address.
AEN/WR
22
12
Outputs high level when the start address of a message stored
in the directory area of data memory, is being read out.
Determines the timing that higher 8 bits of the external ROM
address are externally latched. They must be latched at the
falling edge of the signal.
ALE
25
15
Output
MD
34
21
Input
set at high-level.
Start signal input.
When ST goes low while CS is at low level, the
μ
PD7759 starts
synthesizing the message specified by I0 to I7. In standby
mode, this signal resets the standby mode and starts speech
synthesis.
ST
35
22
Input
Chip select signal input.
ST becomes valid when CS goes low.
A0
A1
A2
A3
A4
A5
A6
A7
A8
41
42
43
44
45
47
48
49
50
26
27
28
29
30
31
32
33
34
Output
Outputs the lower 9 bits of the external ROM address.
ASD0
ASD1
ASD2
ASD3
ASD4
ASD5
ASD6
ASD7
51
2
3
4
5
8
9
10
35
36
37
38
39
1
2
3
(1) Outputs the higher 8 bits of external ROM address.
(2) Inputs 8-bit speech synthesis data from the external ROM.
These functions are executed from (1) to (2) on a time-
shared basis.
Input/
Output
SAA
23
13
Output
CS
38
25
Input
Input
Output/
Input
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