參數(shù)資料
型號(hào)： UPD78F9200MA-CAC-A
廠商： Renesas Electronics America
文件頁數(shù)： 49/158頁
文件大小： 0K
描述： MCU 8BIT 1KB FLASH MEM 10-SSOP
標(biāo)準(zhǔn)包裝： 1
系列： 78K0S/Kx1+
核心處理器： 78K0S
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 7
程序存儲(chǔ)器容量： 1KB（1K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 10-LSSOP（0.225"，5.72mm 寬）
包裝： 托盤
其它名稱： 972-1044
UPD78F9200MA-CAC-A-ND
CHAPTER 7 8-BIT TIMER H1
User’s Manual U18172EJ3V0UD
140
7.4.2
Operation as PWM output mode
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register
during timer operation is prohibited.
8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register
during timer operation is possible.
The operation in PWM output mode is as follows.
TOH1 output becomes active and 8-bit timer counter H1 is cleared to 0 when 8-bit timer counter H1 and the
CMP01 register match after the timer count is started. TOH1 output becomes inactive when 8-bit timer counter H1
and the CMP11 register match.
(1) Usage
In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.
<1>
Set each register.
Figure 7-9. Register Setting in PWM Output Mode
(i)
Setting timer H mode register 1 (TMHMD1)
0
0/1
1
0
0/1
1
TMMD10 TOLEV1
TOEN1
CKS11
CKS12
TMHE1
TMHMD1
CKS10
TMMD11
Timer output enabled
Timer output level inversion setting
PWM output mode selection
Count clock (fCNT) selection
Count operation stopped
(ii) Setting CMP01 register
Compare value (N): Cycle setting
(iii) Setting CMP11 register
Compare value (M): Duty setting
Remark
00H
≤ CMP11 (M) < CMP01 (N) ≤ FFH
<2>
The count operation starts when TMHE1 = 1.
<3>
The CMP01 register is the compare register that is to be compared first after count operation is enabled.
When the values of 8-bit timer counter H1 and the CMP01 register match, 8-bit timer counter H1 is cleared,
an interrupt request signal (INTTMH1) is generated, and TOH1 output becomes active. At the same time,
the compare register to be compared with 8-bit timer counter H1 is changed from the CMP01 register to the
CMP11 register.
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