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參數(shù)資料
| 型號： | UPSD3214AV-24T1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和64Kbit SRAM的 |
| 文件頁數(shù)： | 102/176頁 |
| 文件大小： | 1081K |
| 代理商： | UPSD3214AV-24T1T |
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μ
PSD323X
102/176
PSD MODULE
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The PSD Module provides configurable
Program and Data memories to the 8032 CPU
core (MCU).In addition, it has its own set of I/O
ports and a PLD with 16 macrocells for general
logic implementation.
I
Ports A,B,C, and D are general purpose
programmable I/O ports that have a port
architecture which is different from the I/O ports
in the MCU Module.
I
The PSD Module communicates with the MCU
Module through the internal address, data bus
(AO-A15, DO-D7)and control signals (RD, WR,
PSEN, ALE, RESET). The user defines the
Decoding PLD in the PSDsoft Development
Tool and can map the resources in the PSD
Module to any program or data address space.
Figure 50 shows the functional blocks in the
PSD Module.
Functional Overview
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1 or 2 Mbit Flash memory. This is the main
Flash memory. It is divided into eight equal-
sized blocks that can be accessed with user-
specified addresses.
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Secondary 256 Kbit Flash boot memory. It is
divided into four equal-sized blocks that can be
accessed with user-specified addresses. This
secondary memorybrings theability to execute
code and update the main Flash concurrently.
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64 Kbit SRAM. The SRAM’s contents can be
protected froma power failureby connecting an
external battery.
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CPLD with 1G Output Micro Cells (OMCs} and
24 Input Micro Cells (IMCs). The CPLD may be
used to efficiently implement a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters.
I
Decode PLD (DPLD) thatdecodes address for
selection of memory blocks in the PSD Module.
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Configurable I/O ports (Port A,B,C and D) that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– I/O ports may be configured as open-drain
outputs.
I
Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you canprogram a blank device orreprogram a
device in the factory or the field.
I
Internal page register that can be used to
expand the 8032 MCU Module address space
by a factor of 256.
I
Internal programmable Power Management
Unit (PMU) that supports a low-power mode
called Power-down Mode. The PMU can
automatically detect a lack of the 8032 CPU
core activity and put the PSD Module into
Power-down Mode.
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Erase/WRITE cycles:
– Flash memory - 100,000 minimum
– PLD - 1,000 minimum
– Data Retention: 15 year minimum (for Main
Flash memory, Boot, PLD and Configuration
bits)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3214AV-24T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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| UPSD3214AV-24U1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3214AV-24U1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3214AV-24U6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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