參數(shù)資料
型號: UPSD3214AV-24T1T
廠商: 意法半導體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
中文描述: 閃存可編程系統(tǒng)設備與8032微控制器核心和64Kbit SRAM的
文件頁數(shù): 82/176頁
文件大?。?/td> 1081K
代理商: UPSD3214AV-24T1T
μ
PSD323X
82/176
Master receiver mode flow.
1. Read SxSTA.
2. If BBUSY == 1 then
go to step1.
Else then
write slave address to SxDAT and set both
ENI1 and STA, reset AA in SxCON.
3. Wait for interrupt.
4. Read SxSTA.
If BLOST == 1 or /ACK_REP == 1 then
write dummy data to SxDAT
Go to step1.
Else then
clear STA and write FFH to SxDAT.
Set AA in SxCON.
5. Wait for interrupt.
6. Read SxSTA.
If this datum == LAST then
reset AA* and read SxDAT**.
Go to step7.
Else then
read SxDAT**.
Go to step5.
7. Wait for interrupt.
Read SxSTA.
Read SxDAT**.
Note: 1. (*) If the master want to terminate the current data re-
quests, it don’t have to acknowledge to the slave.
2. (**) This action should be the last.
Slave transmitter mode.
1. Write slave address to SxADR, set AA and ENI
in SxCON.
2. Wait for interrupt.
3. Read SxSTA and write FFH to SxDAT*.
4.
5. Wait for interrupt.
6. Read SxSTA.
If STOP == 1 then
Go to step7.
Else then
read data from SxDAT*.
Go to step5.
7. Read dummy data from SxDAT*.
Note: 1. (*) This action should be the last.
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