參數(shù)資料
型號: UPSD3254B-40U1T
廠商: 意法半導(dǎo)體
英文描述: Two and Three Channel Codewheels
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和256Kbit的SRAM
文件頁數(shù): 84/176頁
文件大?。?/td> 1214K
代理商: UPSD3254B-40U1T
μPSD325X DEVICES
84/176
Special Function Register for the DDC Interface
There are eight SFR in the DDC interface:
RAMBUF, DDCCON, DDCADR, DDCDAT are
DDC registers.
S1CON, S1STA, S1DAT, S1ADR are I
2
C Inter-
face registers, same as the ones described in the
standalone I
2
C bus.
DDCDAT Register.
DDC1 DATA register for
transmission (DDCDAT: 0D5H)
I
8-bit READ and WRITE register.
I
Indicates DATA BYTE to be transmitted in
DDC1 protocol.
DDCADR Register.
Address pointer for DDC in-
terface (DDCADR: 0D6H)
I
8-bit READ and WRITE register.
I
Address pointer with the capability of the post
increment. After each access to RAMBUF
register (either by software or by hardware
DDC1 interface), the content of this register will
be increased by one. It’s available both in
DDC1, DDC2 (DDC2B, DDC2B+, and
DDC2AB) and system operation.
Table 60. DDC SFR Memory Map
SFR
Addr
Reg
Name
Bit Register Name
Reset
7
6
5
4
3
2
1
0
D4
RAMBUF
XX
DDC Ram
Buffer
D5
DDCDAT
00
DDC Data
xmit register
D6
DDCADR
00
Addr pointer
register
D7 DDCCON
EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT
M0
00
DDC Control
Register
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