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參數(shù)資料
| 型號： | UT54ACTS74-UVCH |
| 元件分類： | 鎖存器 |
| 英文描述： | ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14 |
| 封裝： | FP-14 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 34K |
| 代理商： | UT54ACTS74-UVCH |
49
RadHard MSI Logic
UT54ACS74/UT54ACTS74
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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