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參數(shù)資料
| 型號(hào)： | UT61256C |
| 英文描述： | ASYNCHRONOUS STATIC RAM- High Speed |
| 中文描述： | 異步靜態(tài)RAM高速 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大小： | 96K |
| 代理商： | UT61256C |
UTRON
UT61256C
Rev. 1.4
32K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC.
P80031
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
tRC
Address
DOUT
Data Valid
tAA
tOH
READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)
t RC
t AA
t ACE
t OE
t CHZ
t OHZ
t CLZ
t OH
t OLZ
HIGH-Z
Data Valid
HIGH-Z
Address
CE
OE
Dout
Notes :
1.
WE is HIGH for read cycle.
2.
Device is continuously selected CE =VIL.
3.
Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.
4.
OE is LOW.
5.
tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured
500mV from steady state.
6.
At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.
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