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參數(shù)資料
| 型號： | UT7Q512-UPA |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| 封裝： | CERAMIC, FP-32 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 142K |
| 代理商： | UT7Q512-UPA |
10
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle.
2. Either E1 scenario above can occur.
3. G high for tAVAV cycle.
A(18:0)
Figure 4b. SRAM Write Cycle 2: Chip Enable - Controlled Access
W
E1
D(7:0)
APPLIED DATA
E1
Q(7:0)
tWLQZ
tETEF
tWLEF
tDVEF
tAVAV3
tAVET
tETEF
tEFAX
or
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