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參數(shù)資料
| 型號： | V23815-U1306-M130 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, XFO72 |
| 封裝： | SMD-72 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 267K |
| 代理商： | V23815-U1306-M130 |
Fiber Optics
V23814/15-U1306-M130 Parallel Optical Link: PAROLI
Tx/Rx AC, 1.6 Gbit/s
5
DESCRIPTION
Receiver V23815-U1306-M130
The PAROLI receiver module converts parallel optical input
signals into parallel electrical output signals. The optical signals
received are converted into voltage signals by PIN diodes,
transimpedance amplifiers, and gain amplifiers. All output data
signals are Low Voltage Differential Signals (LVDS). The data
rate is 250-1600 Mbit/s for each channel. Optical input data
should be DC balanced within 144 bits. The maximum time
interval of consecutive 0’s and 1’s (run length) should not
exceed 72 bits. This will ensure that the output jitter values
given for the transmitter and receiver in this data sheet will be
met. Otherwise, jitter values might be exceeded.
Additional Signal Detect outputs (SD1 active high / SD12 active
low) show whether an optical AC input signal is present at data
input 1 and/or 12. The signal detect circuit can be disabled with
a logic low at ENSD. The disabled signal detect circuit will
permanently generate an active level at Signal Detect outputs,
even if there is insufficient signal input. This could be used for
test purposes.
A logic low at LVDS Output Enable sets all data outputs to logic
low. SD outputs will not be effected.
All nondata signals have LVCMOS levels. Transmission delay of
the PAROLI system is at a maximum 1 μs for the transmitter,
1 μs for the receiver and approximately 5 ns per meter for the
fiber optic cable.
Figure 3. Receiver block diagram
TECHNICAL DATA
Recommended Operating Conditions
Notes
Voltages refer to V
EE
=0 V.
1. Noise frequency: 1 kHz to 1 MHz.
2. Noise frequency: 1 MHz to 1 GHz.
3. Measured between 0.8 V and 2.0 V.
4.
20%–80% level.
Receiver Electro-Optical Characteristics
Pin
Diode
Array
LVDS
Output
Stage
12
12
Data out
Data
Optical
Input
Electrical
Outputs
12
Gain
Amplifier
Signal
Detect
Circuit
12
Amplifier
LVDS Output Enable
ENSD
SD1
-SD12
Parameter
Symbol
Min
Max
Units
Power Supply Voltage
Noise on Power Supply
(1)
Noise on Power Supply
(2)
V
CC
N
PS
1
N
PS2
R
t
3.0
3.6
V
10
mV
100
Differential LVDS
Termination Impedance
80
120
LVCMOS Input
High Voltage
V
LVCMOSIH
2.0
V
CC
V
LVCMOS Input
Low Voltage
V
LVCMOSIL
V
EE
0.8
LVCMOS Input
Rise/Fall Time
(3)
t
R
, t
F
20
ns
Optical Input
Rise/Fall Time
(4)
t
R
, t
F
400
ps
Input Extinction Ratio
ER
λ
C
5.0
dB
Input Center Wavelength
820
860
nm
Parameter
Symbol
Min. Typ. Max.
Units
Supply Current
l
CC
P
250
350
mA
Power Consumption
0.8
1.3
W
LVDS Output
Low Voltage
(1,4)
V
LVDSOL
925
mV
LVDS Output
High Voltage
(1,4)
V
LVDSOH
1475
LVDS Output
Differential
Voltage
(1, 2, 4)
|
V
OD
|
250
400
LVDS Output
Offset Voltage
(1, 3, 4)
LVDS Rise/Fall Time
(5)
V
OS
1125
1275
t
R
, t
F
I
LVCMOSOL
400
ps
LVCMOS Output
Voltage Low
400
mV
LVCMOS Output
Voltage High
I
LVCMOSOH
2500
LVCMOS Input
Current High/Low
LVCMOS Output
(8)
Current High
LVCMOS Output
(9)
Current Low
Random Jitter
(6, 7)
(14
σ
)
Deterministic Jitter
(6)
I
LVCMOSI
–500
500
μ
A
I
LVCMOSOH
0.5
mA
I
LVCMOSOL
4.0
J
R
0.31
UI
J
D
t
CSK
0.08
Channel-to-channel
skew
(10)
75
ps
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