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參數(shù)資料
| 型號： | V23815-U1306-M130 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, XFO72 |
| 封裝： | SMD-72 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 267K |
| 代理商： | V23815-U1306-M130 |
Fiber Optics
V23814/15-U1306-M130 Parallel Optical Link: PAROLI
Tx/Rx AC, 1.6 Gbit/s
7
Optical Port
Designed for Infineon Simplex MT Connector (SMC)
Port outside dimensions: 15.4 mm x 6.8 mm (width x height)
MT compatible fiber spacing (250
μ
m) and alignment pin
spacing (4600
μ
m)
Alignment pins fixed in module port
Integrated mechanical keying
process plug (SMC dimensions) included with every module
cleaning of port and connector interfaces necessary prior
to mating
Features of Infineon Simplex MT Connector (SMC)
(as part of optional PAROLI fiber optic cables)
Uses standardized MT ferrule
MT compatible fiber spacing (250
μ
m) and alignment pin
spacing (4600
μ
m)
Snap-in mechanism
Ferrule bearing spring loaded
Not strain-relieved
Integrated mechanical keying
Cleaning and Soldering Process for
Transmitter and Receiver
Special care must be taken to remove residuals from the sol-
dering and washing process, which can impact the mechanical
function. Avoid the use of aggressive organic solvents like
ketones, ethers, etc. Consult the supplier of the PAROLI mod-
ules and the supplier of the solder paste and flux for recom-
mended cleaning solvents.
The following common cleaning solvents will not affect the
module: deionized water, ethanol, and isopropyl alcohol. Air-
drying is recommended to a maximum temperature of 100°C.
Do not use ultrasonics.
During soldering, heat must be applied to the leads only, to
ensure that the case temperature never exceeds 100°C. The
module must be mounted with a hot-bar soldering process
using a SnPb solder type, e.g.. S-Sn63Pb37E, in accordance
with ISO 9435.
23
V
EE
V
EE
t.b.l.o.
Ground
24
Ground
25
to be left open
26
DO04P
LVDS Out
Data Output #4, non-inverted
27
DO04N
LVDS Out
Data Output #4, inverted
28
V
EE
DO05P
Ground
29
LVDS Out
Data Output #5, non-inverted
30
DO05N
LVDS Out
Data Output #5, inverted
31
V
EE
V
EE
DO06P
Ground
32
Ground
33
LVDS Out
Data Output #6, non-inverted
34
DO06N
LVDS Out
Data Output #6, inverted
35
V
EE
V
EE
DO07P
Ground
36
Ground
37
LVDS Out
Data Output #7, non-inverted
38
DO07N
LVDS Out
Data Output #7, inverted
39
V
EE
V
EE
DO08P
Ground
40
Ground
41
LVDS Out
Data Output #8, non-inverted
42
DO08N
LVDS Out
Data Output #8, inverted
43
V
EE
V
EE
V
EE
DO09P
Ground
44
Ground
45
Ground
46
LVDS Out
Data Output #9, non-inverted
47
DO09N
LVDS Out
Data Output #9, inverted
48
t.b.l.o.
to be left open
49
V
EE
V
EE
DO10P
Ground
50
Ground
51
LVDS Out
Data Output #10, non-inverted
52
DO10N
LVDS Out
Data Output #10, inverted
53
V
EE
V
EE
DO11P
Ground
54
Ground
55
LVDS Out
Data Output #11, non-inverted
56
DO11N
LVDS Out
Data Output #11, inverted
57
V
EE
V
EE
DO12P
Ground
58
Ground
59
LVDS Out
Data Output #12, non-inverted
60
DO12N
LVDS Out
Data Output #12, inverted
61
V
EE
V
EE
V
EE
t.b.l.o.
Ground
62
Ground
63
Ground
64
to be left open
65
V
EE
V
CC3
Ground
66
Power supply voltage of digital
circuitry
Pin#
Pin Name
Level/Logic Description
67
-SD12
LVCMOS
Out
low active
Signal Detect on fiber #12
Low=signal of sufficient AC
power is present on fiber #12
High=signal on fiber #12 is
insufficient
68
ENSD
LVCMOS In High=SD1 and SD12 function
enabled
Low=SD1 and SD12 are set to
permanent active.Internal pull-
up pulls to high level when in-
put is left open.
69
t.b.l.o.
to be left open
70
V
CC2
Power supply voltage of LVDS
outputs
71
V
CC1
Power supply voltage of ampli-
fier
72
V
EE
Ground
Pin#
Pin Name
Level/Logic Description
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