參數(shù)資料
型號(hào)： V23832-T2431-M101
廠商： INFINEON TECHNOLOGIES AG
英文描述： PAROLI 2 Tx AC, 1.25 Gbit/s
中文描述： 帕羅利2個(gè)發(fā)送，1.25千兆交流/秒
文件頁(yè)數(shù)： 9/33頁(yè)
文件大?。?/td> 709K
代理商： V23832-T2431-M101
V23832-T2531-M101
V23832-R511-M101
Description
Data Sheet
9
2003-11-19
Receiver V23832-R511-M101
The PAROLI receiver module converts parallel optical input signals into parallel electrical
output signals. The optical signals received are converted into voltage signals by PIN
diodes, trans impedance amplifiers, and gain amplifiers. The differential data outputs are
Infineon’s adjustable CML signals. A separate module (V23832-R521-M101) with LVDS
output is also available. The output differential voltage (swing) is adjusted by an external
resistor connected to the REFR module input, the output average is adjustable by
external pull-up resistors.
The data rate is up to 1250 Mbit/s for each channel. The receiver module’s min. data rate
of 500 Mbit/s is specified for the CID
1)
worst case pattern (disparity 72) or any pattern
with a lower disparity.
Additional Signal Detect outputs (SD1 active high / –SD12 active low) show whether an
optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can
be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently
generate an active level at Signal Detect outputs, even if there is insufficient signal input.
This could be used for test purposes.
A logic low at Output Enable sets all data outputs to logic low. SD outputs will not be
effected.
All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is
≤
1 ns for the transmitter,
≤
1 ns for the receiver and approximately 5 ns per meter for
the fiber optic cable.
Figure 5
Receiver Block Diagram
1)
Consecutive Identical Digit (CID) immunity test pattern for STM-N signals,
ITU-T recommendation G.957 sec. II.
Pin
Diode
Array
CML
Output
Stage
12
12
Data Out
REFR
Data
Optical
Input
Electrical
Output
12
Gain
Amplifier
Signal
Detect
Circuit
12
Amplifier
Output Enable (OEN)
ENSD
SD1
SD12
File: 3323
相關(guān)PDF資料
PDF描述
V23833-F0005-B101 XFP850 nm Small Form Factor Module 10 Gigabit Pluggable Transceiver Compatible with XFP MSA Rev. 3.1
V23833-F0005-B102 XFP850 nm Small Form Factor Module 10 Gigabit Pluggable Transceiver Compatible with XFP MSA Rev. 3.1
V23833-F9909-Z001 10 Gigabit XFP SerialHot-Pluggable Transceiver
V23833-FX105-B001 XFP1310 nm Small Form Factor Module 10 Gigabit Pluggable Transceiver Compatible with XFP MSA Rev. 3.1
V23833-G2104-A001 XPAK 1310 nm Module 10 Gigabit Pluggable Transceiver Compatible with XPAK MSA Rev. 2.3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
V23832-T2531-M101 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:PAROLI 2 Tx AC, 1.25 Gbit/s
V23833-D6005-A001 功能描述:TRANSCEIVER 850NM 10G ETHERNET RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件
V23833-D9909-Z100 制造商:Infineon Technologies AG 功能描述:CAGE ASSEMBLY KIT
V23833-F0005-B101 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:XFP850 nm Small Form Factor Module 10 Gigabit Pluggable Transceiver Compatible with XFP MSA Rev. 3.1
V23833-F0005-B102 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:XFP850 nm Small Form Factor Module 10 Gigabit Pluggable Transceiver Compatible with XFP MSA Rev. 3.1
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*