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參數(shù)資料
| 型號(hào)： | V30208TSS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ultra Low Power 1-Bit 32 kHz RTC |
| 中文描述： | 超低功耗1位32 kHz的時(shí)鐘 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 470K |
| 代理商： | V30208TSS |
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Test
From the various test features added to the V 3020 some may
be activated by the user. Table 7a shows the test mode bits.
Table 8 shows the 3 available test modes and how they can be
activated. Test mode 0 is activated by setting bit 2, address 0,
and causes all time keeping to be accelerated by 32. Test mode
1 is activated by setting bit 3, address 0, and causes all the time
and date locations, address 2 to address 9, to be incremented
in parallel at 1 Hz with no carry over (independent of each
other). The third test mode combines the previous two resulting
in parallel incrementing at 32 Hz.
An external signal generator can be used to drive the divider
chain of the V3020. Fig. 13a and 13b show how to connect the
signal generator. The speed can be increased by increasing the
signal generator frequency to a maximum of 128 kHz. An
external signal generator and test modes can be combined.
To leave test both test bits (address 0, bits 2 and 3) must be
cleared by software. Test corrupts the current time and date and
so the time and date should be reloaded after a test session.
Note :
The peak value of the signal provided by the signal
generator should not exceed 1.5 V on XO.
Access Considerations
The section “Communication Cycles” describes the serial data
sequences necessary to complete a communication cycle. In
common with all serial peripherals, the serial data sequences
are not re-entrant, thus a high priority interrupt, or another
software task, should not attempt to access the V3020 if it is
already in the middle of a cycle. A semaphore (software flag) on
access would allow the V3020 to be shared with other software
tasks or interrupt routines. There is not time limit on the duration
of a communication cycle and thus interrupt routines (which do
not use the V3020) can be fully executed in mid cycle without
any consequences for the V3020.
Note :
The peak value of the signal provided by the signal
generator should not exceed 1.5 V on XO.
Crystal Layout
In order to ensure proper oscillator operation we recommend
the following standard practices.
- Keep traces as short as possible.
- Use a guard ring around the crystal.
Fig. 14 shows the recommended layout.
12
Test Modes
Table 8
Addr. 0
bit 3
0
0
1
Addr. 0
bit 2
0
1
0
1
Normal operation
All time keeping accelerated by 32
Parallel increment of all time
data at 1 Hz with no carry over
Parallel increment of all time data
at 32 Hz with no carry over
1
Function
0 - 5.5 V
XI
XO
V3020
1)
100 k
W
1)
36 k
W
1)
indicative values
Fig. 13b
V
SS
Oscillator Layout
XI
XO
V
ss
CS
Fig. 14
V3020
Signal Generator Connection
1 - 1.5 V
Fig. 13a
V
SS
XI
XO
V3020
peak to peak
V3020
R
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