- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359318 > V30208TSS (Electronic Theatre Controls, Inc.) Ultra Low Power 1-Bit 32 kHz RTC PDF資料下載
參數(shù)資料
| 型號： | V30208TSS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ultra Low Power 1-Bit 32 kHz RTC |
| 中文描述： | 超低功耗1位32 kHz的時鐘 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 470K |
| 代理商： | V30208TSS |
Functional Description
Serial Communication
The V3020 resides on the parallel data and address buses as a
standard peripheral (see Fig. 15 and 16). Address decoding
provides an active low chip select (CS) to the device. For Intel
compatible bus timing the control signals RD and WR pulse and
CS are used for a single bit read or write (see Fig. 7a and 7b).
Two options exist for Motorola compatible bus timing. The first
is to use the control signals DS with R/W and CS, the second is
to tie the RD input to CS and use the control signals R/W and CS
(see Fig. 7a and 7c). Data transfer is accomplished through a
single input / output line (I/O). Any data bus line can be chosen.
A conventional 3 wire serial interface can also be used to
communicate with the V3020 (see Fig. 17).
Communication Cycles
The V3020 has 3 serial communication cycles. These are :
1) Read data cycle
2) Write data cycle
3) Address command cycle
A communication cycle always begins by writing the 4 address
bits, A0 to A3. A microprocessor read from the V3020 cannot
begin a communication cycle. Read and write data cycles are
similar and consist of 4 address bits and 8 data bits. The 4
address bits, A0 to A3, define the RAM location and the 8 data
bits D0 and D7, provide the relevant information. An address
command cycle consists of only 4 address bits.
Read Data Cycle
A read data cycle commences by writing the 4 RAM address
bits (A3, A2, A1 and A0) to the V3020. The LSB, A0, is
transmitted first (see Fig. 8a and 8b). Eight microprocessor
reads from the V3020 will read the RAM data at this address,
beginning with the LSB, D0. The read data cycle finishes on
reading the 8th data bit, D7.
Write Data Cycle
A write data cycle commences by writing the 4 RAM address
bits (A3, A2, A1 and A0) to the V3020. The LSB, A0, is
transmitted first (see Fig. 8c and 8d). Eight microprocessor
writes to the V3020 will write the new RAM data. The LSB, D0, is
loaded first. The write data cycle finishes on writing the 8th data
bit, D7.
9
Address Command Cycle
An address command cycle consists of just 4 address bits. The
LSB, A0, is transmitted first (see Fig. 8e and 8f). On writing the
fourth address bit, A3, the address will be decoded. If the
address bits are recognized as one of the command codes E
hex or F hex (see Table 6), then the communication cycle is
terminated and the corresponding command is executed.
Subsequent microprocessor writes to the V3020 begin another
communication cycle with the first bit being interpreted as the
address LSB, A0.
Clock Configuration
The V3020 has a reserved clock area and a user RAM area (see
Fig. 9). The clock is not directly accessible, it is used for internal
time keeping and contains the current time and date. The
contents of the RAM is shown in Table 6, it contains a data space
and an address command space. The data space is directly
accessible. Addresses 0 and 1 contain status information ( see
Tables 7a and 7b), addresses 2 to 5, time data, and addresses 6
to 9, date data. The address command space is used to issue
commands to the V3020.
RAM Map
Commands
Two commands are available (see Table 6). The
Copy_RAM_to_clock command is used to set the current time
and date in the clock and the Copy_clock_to_RAM command to
copy the current time and date from the clock to the RAM. The
Copy_RAM_to_clock command, address data E hex, causes
the clock time and date to be overwritten by the time and date
stored in the RAM at addresses 2 to 9. Address 1 is also cleared
(see section “Time and Date Status Bits”). Prior to using this
command, the desired time and date must be loaded into the
RAM using write data cycles and the time set lock bit, address 0,
bit 7, must be clear (see section “Time Set Lock”).
Table 6
0
1
2
3
4
5
6
7
8
9
14
15
0
1
2
3
4
5
6
7
8
9
E
F
Status 0
Status 1
Seconds
Minutes
Hours
Day of month
Month
Year
Week day
Week number
Copy_RAM_to_clock
Copy_clock_to_RAM
00-59
00-59
00-23
01-31
01-12
00-99
01-07
00-52
Parameter
BCD
range
Dec Hex
Data Space
Address
Address Command Space
Pin Description
Table 5
Pin
1
2
3
4
5
6
7
8
XI
XO
CS
V
SS
I/O
RD
WR
V
DD
32 kHz crystal input
32 kHz crystal output
Chip select input
Ground supply
Data input and output
Intel RD, Motorola DS (or tie to CS)
Intel WR, Motorola R/W
Positive supply
Name
Function
SO8 TSSO8
3
4
5
6
7
8
1
2
V3020
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V3021 | Ultra Low Power 1-Bit 32 kHz RTC |
| V30218P | Ultra Low Power 1-Bit 32 kHz RTC |
| V30218S | Ultra Low Power 1-Bit 32 kHz RTC |
| V302AS32 | High Energy Metal-Oxide Arrester Blocks |
| V31CP20 | Tubular Metal-Oxide Varistors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V3020SO8A | 制造商:EMMICRO 制造商全稱:EM Microelectronic - MARIN SA 功能描述:Ultra Low Power 1-Bit 32 kHz RTC |
| V3020SO8B | 制造商:EMMICRO 制造商全稱:EM Microelectronic - MARIN SA 功能描述:Ultra Low Power 1-Bit 32 kHz RTC |
| V3020TP8A | 制造商:EMMICRO 制造商全稱:EM Microelectronic - MARIN SA 功能描述:Ultra Low Power 1-Bit 32 kHz RTC |
| V3020TP8B | 制造商:EMMICRO 制造商全稱:EM Microelectronic - MARIN SA 功能描述:Ultra Low Power 1-Bit 32 kHz RTC |
| V3020XSO8A | 制造商:EMMICRO 制造商全稱:EM Microelectronic - MARIN SA 功能描述:Ultra Low Power 1-Bit 32 kHz RTC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。