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參數(shù)資料
| 型號： | V370PDC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit |
| 中文描述： | 高性能PCI SDRAM控制器的集成了外圍控制單元 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 99K |
| 代理商： | V370PDC |
V370PDC
14
V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101
Copyright 1999, V3 Semiconductor Inc.
3.6
Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms
generated are shown in Figure 4.
Figure 4: Serial EEPROM Waveforms and Timings
4.0 Revision History
USA:
2348G Walsh Avenue
Santa Clara, CA 95051
Phone: (408)988-1050 Fax: (408)988-2601
Toll Free: (800)488-8410 (Canada and U.S. only)
World Wide Web: http://www.vcubed.com
Table 14: Revision History
Revision
Number
Date
Comments and Changes
0.8
01/99
First pre-silicon revision of preliminary data sheet.
0.9
03/99
Update Figure 2: Mechanical Drawing;
Update Table 8: Local Bus Signals DC Operating Specifications;
Update Table 10: Local Bus AC Test Conditions;
Update Table 12: Local Bus Signals AC Operating Specifications.
1.0
03/99
Initial Release.
1.1
06/00
Updated TBA parameters
SCL
SDA
START CONDITION
STOP CONDITION
512 PCI BUS
CLOCKS
256 PCI BUS
CLOCKS
256 PCI BUS
CLOCKS
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| V370PDC-66 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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