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參數(shù)資料
| 型號(hào)： | V437464Q24VBTG-10PC |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大小： | 322K |
| 代理商： | V437464Q24VBTG-10PC |
MOSEL VITELIC
V437464Q24V
9
V437464Q24V Rev. 1.0 January 2002
AC Characteristics 3,4
TA =0° to 70°C; VSS =0V; VCC =3.3V ± 0.3V, tT =1ns
#
Symbol Parameter
Limit Values
Unit
Note
-75PC
-75
-10PC
Min.
Max.
Min.
Max.
Min.
Max.
Clock and Clock Enable
1tCK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
10
ns
2fCK
System frequency
CAS Latency = 3
CAS Latency = 2
–
133
–
133
100
–
100
MHz
3tAC
ClockAccessTime
CAS Latency = 3
CAS Latency = 2
–
5.4
–
5.4
6
–
6
ns
2, 4
4tCH
Clock High Pulse Width
2.5
–
2.5
–
3
–
ns
6
5tCL
Clock Low Pulse Width
2.5
–
2.5
–
3
–
ns
6
6tCS
Input Setup time
1.5
–
1.5
–
2
–
ns
7
7tCH
Input Hold Time
0.8
–
0.8
–
1
–
ns
7
8tCKSP
CKE Setup Time (Power down mode)
2
–
2
–
2
–
ns
8
9tCKSR
CKE Setup Time (Self Refresh Exit)
8
–
8
–
8
–
ns
9
10
tT
Transition time (rise and fall)
1
–
1
–
1
–
ns
Common Parameters
11
tRCD
RAS to CAS delay
15
–
20
–
20
–
ns
6
12
tRC
Cycle Time
60
120K
60
120K
70
120K
ns
6
13
tRAS
Active Command Period
42
–
45
–
45
–
ns
6
14
tRP
Precharge Time
15
–
20
–
20
–
ns
6
15
tRRD
Bank to Bank Delay Time
14
–
15
–
16
–
ns
6
16
tCCD
CAS to CAS delay time (same bank)
1
–
1
–
1
–
CLK
Refresh Cycle
17
tSREX
Self Refresh Exit Time
10
–
10
–
10
–
ns
18
tREF
Refresh Period (8192 cycles)
64
–
64
–
64
–
ms
Read Cycle
19
tOH
Data Out Hold Time
3
–
3
–
3
–
ns
2, 4
20
tLZ
Data Out to Low Impedance Time
0
–
0
–
0
–
ns
21
tHZ
Data Out to High Impedance Time
3
7.5
3
7.5
3
9
ns
10
22
tDQZ
DQM Data Out Disable Latency
2
–
2
–
2
–
CLK
Write Cycle
23
tDPL
Data input to Precharge (write recovery)
2
–
2
–
1
–
CLK
24
tDQW
DQM Write Mask Latency
0
–
0
–
0
–
CLK
11
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