參數(shù)資料
型號(hào): V437464Q24VBTG-10PC
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 64M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 9/13頁
文件大?。?/td> 322K
代理商: V437464Q24VBTG-10PC
MOSEL VITELIC
V437464Q24V
5
V437464Q24V Rev. 1.0 January 2002
Serial Presence Detect Information
A serial presence detect storage device –
E2PROM – is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
writtenintothe E2PROM device during module pro-
duction using a serial presence detect protocol (I2C
synchronous 2-wire bus)
SPD-Table for modules:
Byte Num-
ber
Function Described
SPD Entry Value
Hex Value
-75PC
-75
-10PC
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
13
0D
4
Number of Column Addresses (for x4
SDRAM)
11
0B
5
Number of DIMM Banks
1
01
6
Module Data Width
72
48
7
Module Data Width (continued)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAMCycleTimeat CL=3
7.5ns/10.0ns
75
A0
10
SDRAM Access Time from Clock at CL=3
5.4/6.0 ns
54
60
11
Dimm Config (Error Det/Corr.)
ECC
02
12
Refresh Rate/Type
Self-Refresh, 15.8
s80
80
13
SDRAM width, Primary
x4
04
14
Error Checking SDRAM Data Width
x4
04
15
Minimum Clock Delay from Back to Back
Random Column Address
tccd =1 CLK
01
16
Burst Length Supported
1, 2, 4, 8
0F
17
Number of SDRAM Banks
4
04
18
Supported CAS Latencies
CL = 2, 3
06
19
CS Latencies
CS Latency = 0
01
20
WE Latencies
WL = 0
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg
00
22
SDRAM Device Attributes: General
Vcc tol ± 10%
0E
23
Minimum Clock Cycle Time at CAS Latency
=2
7.5 ns/10.0 ns
75
A0
24
Maximum Data Access Time from Clock for
CL = 2
5.4 ns/6.0 ns
54
60
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
26
Maximum Data Access Time from Clock at
CL = 1
Not Supported
00
27
Minimum Row Precharge Time
15 ns/20 ns
0F
14
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