參數(shù)資料
型號(hào): V53C16256H
廠商: Mosel Vitelic, Corp.
英文描述: 256K x 16 FAST PAGE MODE CMOS DYNAMIC RAM
中文描述: 256K × 16快速頁(yè)面模式的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù): 6/19頁(yè)
文件大小: 146K
代理商: V53C16256H
6
V53C16256H Rev. 2.3 June 1998
MOSEL V ITELIC
V53C16256H
21
t
CL1QX
t
LZ
OE or CAS to
Low-Z Output
0
0
0
0
0
0
ns
16
22
t
CH2QZ
t
HZ
OE or CAS to
High-Z Output
0
5
0
6
0
6
0
7
0
8
0
10
ns
16
23
t
RL1AX
t
AR
Column Address
Hold Time
from RAS
26
28
30
35
40
50
ns
24
t
RL1AV
t
RAD
RAS to Column
Address Delay
Time
10
14
11
17
12
20
13
23
14
26
15
30
ns
11
25
t
CL1RH1(W)
t
RSH (W)
RAS or CAS Hold
Time in Write Cycle
10
10
12
13
14
15
ns
26
t
WL1CH1
t
CWL
Write Command to
CAS Lead Time
10
11
12
13
14
15
ns
27
t
WL1CL2
t
WCS
Write Command
Setup Time
0
0
0
0
0
0
ns
12, 13
28
t
CL1WH1
t
WCH
Write Command
Hold Time
5
5
5
6
7
10
ns
29
t
WL1WH1
t
WP
Write Pulse Width
5
5
5
6
7
10
ns
30
t
RL1WH1
t
WCR
Write Command
Hold Time from
RAS
26
28
30
35
40
50
ns
31
t
WL1RH1
t
RWL
Write Command to
RAS Lead Time
10
11
12
13
14
15
ns
32
t
DVWL2
t
DS
Data in Setup Time
0
0
0
0
0
0
ns
14
33
t
WL1DX
t
DH
Data in Hold Time
5
5
5
6
7
10
ns
14
34
t
WL1GL2
t
WOH
Write to OE Hold
Time
5
5
6
7
8
10
ns
14
35
t
GH2DX
t
OED
OE to Data Delay
Time
5
5
6
7
8
10
ns
14
36
t
RL2RL2
(RMW)
t
RWC
Read-Modify-Write
Cycle Time
100
105
110
115
130
170
ns
37
t
RL1RH1
(RMW)
t
RRW
Read-Modify-Write
Cycle RAS Pulse
Width
65
70
75
80
87
105
ns
38
t
CL1WL2
t
CWD
CAS to WE Delay
26
28
30
32
34
40
ns
12
39
t
RL1WL2
t
RWD
RAS to WE Delay
in Read-Modify-
Write Cycle
50
54
58
62
68
85
ns
12
40
t
CL1CH1
t
CRW
CAS Pulse Width
(RMW)
44
46
48
50
52
65
ns
#
JEDEC
Symbol
Symbol Parameter
30
35
40
45
50
60
Unit Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
AC Characteristics
(Cont’d)
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PDF描述
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