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參數(shù)資料
| 型號： | V53C1668H |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | High Performance 64K X 16 Bit EDO Page Mode Dual CAS CMOS Dynamic RAM(高性能64Kx16EDO頁面模式雙CAS輸入CMOS動態(tài)RAM) |
| 中文描述： | 高性能64K的× 16位EDO公司頁面模式雙中科院的CMOS動態(tài)RAM（高性能64Kx16EDO頁面模式雙中科院輸入的CMOS動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 160K |
| 代理商： | V53C1668H |
6
V53C1668H Rev. 1.1 February 1999
MOSEL V ITELIC
V53C1668H
t
RWL
Write Command to RAS Lead Time
10
11
12
13
14
ns
t
DS
Data in Setup Time
0
0
0
0
0
ns
14
t
DH
Data in Hold Time
5
5
5
6
7
ns
14
t
WOH
Write to OE Hold Time
5
5
6
7
8
ns
14
t
OED
OE to Data Delay Time
5
5
6
7
8
ns
14
t
RWC
Read-Modify-Write Cycle Time
100
105
110
115
130
ns
t
RRW
Read-Modify-Write Cycle RAS
Pulse Width
65
70
75
80
87
ns
t
CWD
CAS to WE Delay
26
28
30
32
34
ns
12
t
RWD
RAS to WE Delay in Read-Modify-
Write Cycle
50
54
58
62
68
ns
12
t
CRW
CAS Pulse Width (RMW)
44
46
48
50
52
ns
t
AWD
Col. Address to WE Delay
32
35
38
41
42
ns
12
t
PC
EDO Page Mode Read or Write
Cycle Time
12
14
15
17
19
ns
t
CP
CAS Precharge Time
3
4
5
6
7
ns
t
CAR
Column Address to RAS Setup
Time
16
18
20
22
24
ns
t
CAP
Access Time from Column
Precharge
19
21
23
25
27
ns
7
t
DHR
Data in Hold Time Referenced
to RAS
26
28
30
35
40
ns
t
CSR
CAS Setup Time CAS- before-RAS
Refresh
10
10
10
10
10
ns
t
RPC
RAS to CAS Precharge Time
0
0
0
0
0
ns
t
CHR
CAS Hold Time CAS-before-RAS Re-
fresh
7
8
8
10
12
ns
t
PCM
EDO Page Mode Read-Modify-
Write Cycle Time
56
58
60
65
70
ns
t
COH
Output Hold After CAS Low
5
5
5
5
5
ns
t
OES
OE Low to CAS HIGH Setup Time
5
5
5
5
5
ns
t
OEH
OE Hold Time from WE during
Read-Modify Write Cycle
10
10
10
10
10
ns
t
OEP
OE High Pulse Width
10
10
10
10
10
ns
t
T
Transition Time (Rise and Fall)
1.5
50
1.5
50
1.5
50
1.5
50
1.5
50
ns
15
t
REF
Refresh Interval (256 Cycles)
4
4
4
4
4
ms
17
Symbol
Parameter
30
35
40
45
50
Unit
Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
AC Characteristics
(Cont’d)
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