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參數(shù)資料
| 型號(hào)： | V53C516400A60 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | TOOLS, HAND CRIMP RoHS Compliant: Yes |
| 中文描述： | 4米× 4快速頁面模式的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 172K |
| 代理商： | V53C516400A60 |
22
V53C516400A Rev. 1.1 March 1998
MOSEL V ITELIC
V53C516400A
Block Diagram in Test Mode
Normal
Test
Vcc
Vss
I/O 3
Normal
Test
Vcc
Vss
I/O 2
Normal
Test
Vcc
Vss
I/O 1
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
I/O 4
I/O 3
I/O 2
I/O 1
Normal
Test
Normal
Normal
Normal
Test
Test
Test
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
Normal
Test
Vcc
Vss
I/O 4
Test Mode
As the V53C516400A is organized internally as
1M x 16-bits, a test mode cycle using 4:1 compres-
sion can be used to improve test time. Note that in
the 4M x 4 version the test time is reduced by 1/4 for
a N test pattern.
In a test mode “write” the data from each I/O pin is
written into four 1M blocks simultaneously (all “1” s
or all “0” s). In test mode “read” each I/O output is
used for indicating the test mode result. If the internal
four bits are equal, the I/O would indicate a “1”. If
they were not equal, the I/O would indicate a “0”. The
WCBR cycle (WE, CAS before RAS) puts the device
into test mode. To exit from test mode, a “CAS be-
fore RAS refresh”, “RAS only refresh” or “Hidden re-
fresh” can be used.Refresh during test mode
operation can be performed by normal read cycles or
by WCBR refresh cycles.
Row addresses A0 through A9 have to kept high
to perform a testmode entry cycle. All other address-
es are don’t care.
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| V53C516400A | 4M x 4 Fast Page Mode CMOS Dynamic RAM(4Mx4快速頁面模式CMOS動(dòng)態(tài)RAM) |
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| V53C516405AK60 | DRAM|EDO|4MX4|CMOS|SOJ|26PIN|PLASTIC |
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