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參數(shù)資料
| 型號： | V53C516405A60 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM |
| 中文描述： | 4米× 4 EDO公司頁面模式的CMOS動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 170K |
| 代理商： | V53C516405A60 |
MOSEL V ITELIC
1
V53C516405A
4M X 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C516405A Rev. 1.1 March 1998
V53C516405A
50
60
Max. RAS Access Time, (t
RAC
)
50 ns
60 ns
Max. Column Address Access Time, (t
CAA
)
25 ns
30 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
20 ns
25 ns
Min. Read/Write Cycle Time, (t
RC
)
84 ns
104 ns
Features
I
4M x 4-bit organization
I
EDO Page Mode for a sustained data rate
of 50 MHz
I
RAS access time: 50, 60, 70 ns
I
Low power dissipation
I
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh
I
Refresh Interval: 4096 cycles/64 ms
I
Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
I
Single +5 V
±
10% Power Supply
I
TTL Interface
Description
The V53C516405A is a 4,194,304 x 4 bit high-
performance CMOS dynamic random access
memory. The V53C516405A offers Page mode
operation with Extended Data Output. The
V53C516405A has a symmetric address, 12-bit row
and 10-bit column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 4 bits,
within a page, with cycle times as short as 20ns.
These features make the V53C516405A ideally
suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
50
60
Std.
0
°
C to 70
°
C
Blank
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V53C516405AK50 | DRAM|EDO|4MX4|CMOS|SOJ|26PIN|PLASTIC |
| V53C516405AK60 | DRAM|EDO|4MX4|CMOS|SOJ|26PIN|PLASTIC |
| V53C516405AT50 | DRAM|EDO|4MX4|CMOS|TSOP|26PIN|PLASTIC |
| V53C516405AT60 | DRAM|EDO|4MX4|CMOS|TSOP|26PIN|PLASTIC |
| V53C516405A | 4M x 4 EDO Page Mode CMOS Dynamic RAM(4Mx4EDO頁面模式CMOS動態(tài)RAM) |
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