參數(shù)資料
型號(hào): V54C3256804VB
廠商: Mosel Vitelic, Corp.
英文描述: 256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
中文描述: 片256Mbit SDRAM的3.3伏,第二的TSOP /系統(tǒng)芯片的BGA / WBGA包裝16米x 16,32 × 8,64米× 4
文件頁數(shù): 8/52頁
文件大?。?/td> 853K
代理商: V54C3256804VB
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
8
V54C3256(16/80/40)4V(T/S/B) Rev1.6 September
Capacitance*
T
A
= 0 to 70
°
C, V
CC
= 3.3 V
±
0.3 V, f = 1 Mhz
*
Note:
Capacitance is sampled and not 100% tested.
Absolute Maximum Ratings*
Operating temperature range..................0 to 70 °C
Storage temperature range................-55 to 150 °C
Input/output voltage.................. -0.3 to (V
CC
+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Symbol
Parameter
Max. Unit
C
I1
Input Capacitance (A0 to A12)
5
pF
C
I2
Input Capacitance
RAS, CAS, WE, CS, CLK, CKE, DQM
5
pF
C
IO
Output Capacitance (I/O)
6.5
pF
C
CLK
Input Capacitance (CLK)
4
pF
Block Diagram
Row decoder
Memory array
Bank 0
8192 x 512
x 16 bit
C
S
Row decoder
Memory array
Bank 1
8192 x 512
x16 bit
C
S
Row decoder
Memory array
Bank 2
8192 x 512
x 16 bit
C
S
Row decoder
Memory array
Bank 3
8192 x 512
x 16 bit
C
S
Input buffer
Output buffer
I/O
1
-I/O
16
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
A0 - A12, BA0, BA1
A0 - A8, AP, BA0, BA1
Control logic & timing generator
C
C
C
R
C
W
L
Row Addresses
Column Addresses
U
x16 Configuration
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