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| 型號： | V54C365404VB |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | High Performance PC100/125MHz 3.3 Volt 16M X 4 Synchronous DRAM(3.3V高性能PC100/125MHz 16Mx4同步動態(tài)RAM) |
| 中文描述： | 高性能PC100/125MHz 3.3伏16米x 4同步DRAM（3.3V的高性能PC100/125MHz 16Mx4同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 9/54頁 |
| 文件大?。?/td> | 475K |
| 代理商： | V54C365404VB |
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MOSEL V ITELIC
V54C365404VB
9
V54C365404VB Rev. 1.1 February 1999
eration. If CA10 is high when a Read Command is
issued, the
Read with Auto-Precharge
initiated. The SDRAM automatically enters the pre-
charge operation one clock before the last data out
for CAS latencies 2, two clocks for CAS latencies 3
and three clocks for CAS latencies 4. If CAS10 is
high when a Write Command is issued, the
with Auto-Precharge
function is initiated. The
SDRAM automatically enters the precharge opera-
tion a time delay equal to t
WR
(Write recovery time)
after the last data in.
function is
Write
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as shown in the following
list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2,
two clocks before the last data out for CAS latency
= 3 and three clocks before the last data out for CAS
latency= 4. Writes require a time delay twr from the
last data out to apply the precharge command.
Bank Selection by Address Bits:
Burst Termination
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate the burst operation prematurely. These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
Driver Operating Options
Note:
The timing parameters are in clk cycle.
A10
BA0
BA1
0
0
0
Bank 0
0
0
1
Bank 1
0
1
0
Bank 2
0
1
1
Bank 3
1
X
X
all Banks
Bus
Frequency 8PC
-8
-10
CL
t
RCD
t
RP
t
RC
100 MHz
X
2
2
2
7
100 MHz
X
3
2
3
8
100 MHz
X
3
2
2
7
100 MHz
X
X
3
3
3
8
66 MHz
X
X
X
2
2
2
7
66 MHz
X
X
X
2
2
3
8
66 MHz
X
X
X
2
2
3
8
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PDF描述 |
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| V54C365404VD | HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4 |
| V54C365804VB | High Performance PC100/125MHz 3.3 Volt 8M X 8 Synchronous DRAM(3.3V高性能pc100/125MHz 8Mx8同步動態(tài)RAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C365404VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4 |
| V54C365804VC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
| V54C365804VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
| V5-5/RK 4-0.3/0.3/0.3 | 制造商:TURCK Inc 功能描述:Cordset, Splitter, M12 Female Straight x 3, 4 Wire, 5m, PVC, Yellow, U0986-00 |
| V5-5/RK 4-1/1/1 | 制造商:TURCK Inc 功能描述:Cordset, Splitter, M12 Female Straight x 3, 4 Wire, 5m, PVC, Yellow, U-16415 |
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