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參數(shù)資料
| 型號： | V59C1512808QAUF19 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 8 DDR DRAM, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 67/79頁 |
| 文件大?。?/td> | 1028K |
| 代理商： | V59C1512808QAUF19 |
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7
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
Self
Idle
Setting
EMRS
Bank
Precharging
Power
Writing
ACT
RDA
Read
SRF
REF
CKEL
MRS
CKEH
CKEL
Write
Automatic Sequence
Command Sequence
RDA
WRA
Read
PR, PRA
PR
Refreshing
Down
Power
Down
Active
with
RDA
Reading
with
WRA
Active
Precharge
Reading
Writing
PR(A) = Precharge (All)
MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
CKEL = CKE low, enter Power Down
CKEH = CKE high, exit Power Down, exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions
Simplified State Diagram
All banks
precharged
Activating
CKEH
Read
Write
CKEL
MRS
CKEL
Sequence
Initialization
OCD
calibration
CKEL
Autoprecharge
PR, PRA
and the commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured
in full detail.
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