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參數(shù)資料
| 型號(hào)： | V6170 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Accurate Voltage Window Surveillance and Software Monitoring |
| 中文描述： | 精確的電壓窗監(jiān)測(cè)及軟件監(jiān)控 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 176K |
| 代理商： | V6170 |
V6170
5
Block Diagram
Pin Description
Pin Name
1
2
RES
Function
Push-pull active low enable output
Open drain active low reset output.
RES must be pulled up to V
DD
even
if unused
Watchdog timer clear input signal
GND terminal
No connection
Voltage supply
R
EXT
input for RC oscillator tuning
Voltage comparator input
Table 5
3
4
5
6
7
8
V
NC
V
DD
R
V
IN
Functional Description
V
IN
Monitoring
The power-on reset and the power-down reset are
generated as a response to the external voltage level on
the V
input. The external voltage level is typically
obtained from a voltage divider as shown in Fig. 9. The
user defines an external voltage divider to set the
desired threshold level for power-on reset and power-
down reset in his system. The internal comparator
reference voltage is typically 1.17 V.
At power-up the reset output (RES)
is held low (see Fig.
5). When V
becomes greater than V
, the RES output
is held low for an additional power-on reset (POR) delay
wich is equal to the watchdog time T
(typically 100 ms
with an external resistor of 118 k
connected at R pin).
The POR delay prevents repeated toggling of RES even
if V
IN
and the INPUT voltage drops out and recovers. The
POR delay allows the microprocessor’s crystal oscillator
time to start and stabilize and ensures correct
recognition of the reset signal to the microprocessor.
The RES output goes active low generating the power-
down reset whenever V
falls below V
. The sensitivity
or reaction time of the internal comparator to the voltage
level on V
IN
is typically 5
μ
s.
Voltage Window
The reset output (RES) is inactive when V
is higher than
V
REF
and when V
is lower than V
. If V
is less than
V
or V
higher than V
HIGH
, the reset output goes active
low (see Fig. 5).
Timer Programming
The on-chip oscillator needs an external resistor R
connected between the R pin and V
(see Fig.
9). It
allows the user to
adjust the power-on reset (POR)
delay, watchdog time T
and with this also the closed
and open time windows as well as the watchdog reset
pulse width (T
WD
/40).
With R
EXT
= 118 k
, the typical delays are:
- Power-on reset delay:
T
POR
is 100 ms
- Watchdog time:
T
WD
is 100 ms
- Closed window:
T
CW
is 80 ms
- Open window:
T
OW
is 40 ms
- Watchdog reset:
T
WOR
is 2.5 ms
Note the current consumption increases as the frequen-
cy increases.
Watchdog Timeout Period Description
The watchdog timeout period is divided into two parts, a
“closed” window and an “open” window (see
Fig. 4) and
is
defined by two parameters, T
WD
and the Open Window
Percentage (OWP).
The closed window starts just after the watchdog timer
EN
TCL
RES
EN
TCL
Fig. 8
V
REF
R
V
IN
Open drain
output RES
Current
Controlled
Oscillator
Voltage
Reference
Enable
Logic
Timer
Reset
Control
+
Comparator
+
Comparator
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