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參數(shù)資料
| 型號： | V6170 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Accurate Voltage Window Surveillance and Software Monitoring |
| 中文描述： | 精確的電壓窗監(jiān)測及軟件監(jiān)控 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 176K |
| 代理商： | V6170 |
V6170
6
resets and is defined by T
= T
OWP(T
).
The open window starts after the closed time window
finishes and lasts till T
+ OWP(T
WD
). The open window
time is defined by T
= 2 x OWP(T
).
For example if T
= 100 ms (actual value) and OWP =
±
20% this means the closed window lasts during first
the 80 ms (T
= 80 ms = 100 ms
0.2 (100 ms)) and
the open window the next 40 ms (T
= 2 x 0.2 (100 ms)
= 40 ms). The watchdog can be serviced between 80
ms and 120 ms after the timer reset. However as the
time base is
±
10% accurate, software must use the
following calculation for servicing signal TCL during the
open window:
Related to curves (Fig. 10 to Fig. 20), especially Fig. 19
and Fig. 20, the relation between T
and R
could
easily be defined. Let us take an example describing the
variations due to production and temperature:
1. Choice, T
= 26 ms.
2. Related to Fig. 20, the coefficient (T
WD
to R
EXT
) is 1.125
where R
is in k
and T
in ms.
3. R
(typ.) = 26 x 1.125 = 29.3 k
.
4. 26 ms at +25
°
C
a)
(26
10% = 23.4 ms) (26 + 10% = 28.6 ms)
a)
b)
(23.4
5% = 22.2 ms) (28.6 + 5% = 30.0 ms)
b)
min.: (30.0
20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)
Typical TCL period of
(24.0 + 26.7) / 2 = 25.4 ms
The ratio between T
WD
= 26 ms and the (TCL period) =
25.4 ms is 0.975.
Then the relation over the production and the full
temperature range is, TCL period = 0.975 x T
WD
or TCL period = 1.125
a) While PRODUCTION value unknown for the custo-
mer when R
≠
118 k
.
b) While operating TEMPERATURE range
40
°
C
≤
T
A
+85
°
C.
5. If you fixed a TCL period = 26 ms
26 x 1.125
R
EXT
0.975
If during your production the T
WD
time can be
measured, at T
= +25
°
C and the
μ
C can adjust
the
TCL period, then
the TCL period range will be much
larger for the full operating temperature.
Timer Clearing and RES Action
The watchdog circuit monitors the activity of the
processor. If the user’s software does not send a pulse
to the TCL input within the programmed open window
timeout period, a short watchdog RES pulse is
generated which is equal to T
WD
/40 = 2.5 ms typically
(see Fig. 6).
With the open window constraint, new security is added
to conventional watchdogs by monitoring both software
cycle time and execution. Should software clear the
watchdog too quickly (incorrect cycle time) or too slowly
(incorrect execution), it will cause the system to be reset.
If the software is stuck in a loop which includes the
routine to clear the watchdog, a conventional watchdog
will not reset the system even though the software is
malfunctioning; the V6170 will generate a system reset
because the watchdog is cleared too quickly.
If no TCL signal is applied before the closed and open
windows expire, RES will start to generate square waves
of period (T
+ T
+ T
). The watchdog will remain
in this state until the next TCL falling edge appears
during an open window, or until a fresh power-up
sequence. The system enable output, EN, can be used
to prevent critical control
functions being activated in the
event of the system going into this failure mode (see
section “Enable
EN Output”).
The RES output must be pulled up to V
even if the
output is not used by the system (see Fig. 9).
Combined Voltage and Timer Action
The combination of voltage and timer actions is
illustrated by the sequence of events shown in Fig. 7. On
power-up, when the voltage at V
reaches V
, the
power-on-reset, POR, delay is initialized and holds RES
active for the time of the POR delay. A TCL pulse will
have no effect until this power-on reset delay is
completed. After the POR delay has elapsed, RES goes
inactive and the watchdog timer starts acting. If no TCL
pulse occurs, RES goes active low for a short time T
after each closed and open window period. A TCL pulse
coming during the open window clears the watchdog
timer. When the TCL pulse occurs too early (during the
closed window), RES goes active and a new timeout
sequence starts. A voltage drop below the V
level for
longer than
typically 5
μ
s, overrides the timer and
immediately forces RES active and EN inactive. Any
further TCL pulse has no effect until the next power-up
sequence has completed.
Enable
EN Output
The system enable output, EN, is inactive always when
RES is active and remains inactive after a RES pulse
until the watchdog is serviced correctly 3 consecutive
times (ie. the TCL pulse must come in the open
window). After three consecutive services of the
watchdog
with TCL during the open window, the EN
goes active low.
A malfunctioning system would be repeatedly reset by
the watchdog. In a conventional system critical motor
controls could be energized each time reset goes
inactive (time allowed for the system to restart) and in
this way the electrical motors driven by the system could
function out of control. The V6170 prevents the above
failure mode by using the EN output to disable the motor
controls until software has successfully cleared the
watchdog three times (ie. the system has correctly
restarted after a reset condition).
0.975 x R
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