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參數(shù)資料
| 型號(hào)： | V63C31364097 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128K X 36 CMOS Synchronous Burst Flow-Through SRAM(128Kx36CMOS同步脈沖流經(jīng)過(guò)的SRAM) |
| 中文描述： | 128K的米鼠36的CMOS同步突發(fā)流量通過(guò)的SRAM（128Kx36CMOS同步脈沖流經(jīng)過(guò)的靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 73K |
| 代理商： | V63C31364097 |
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V63C31364097 Rev. 0.4 February 1999
MOSEL V ITELIC
V63C31364097
AC Operating Conditions and Characteristics
(V
DD
= 3.3V +10%, -5%. T
A
= 0 to 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level......................................................................................... 1.25V
Input Pulse Levels ............................................................................................................................ 0 to 2.5 V
Input Slew Rate (See Note 1)...............................................................................................................1.0V/ns
Output Timing Reference Level.............................................................................................................. 1.25V
Output Load ......................................................................................... See Figure 2 Unless otherwise Noted
Output Rise/Fall Times (max ).................................................................................................................1.8ns
Read/Write Cycle Timing (See Notes 1 and 2)
Notes:
1.
Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high and
SE3 low whenever ADSP or ADSC is asserted
All read and write cycle timings are referenced from K or G.
Tested per AC Test Load, Figure 2.
Measured at
±
200 mV from steady state.
This parameter is sampled and not 100% tested.
2.
3.
4.
5.
Parameter
Symbol
V63C31364097
117 MHz
V63C31364097
100 MHz
V63C31364097
90 MHz
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
Cycle Time
t
KHKH
t
KHKL
t
KLKH
t
KHQV
t
GLQV
t
KHQX1
t
KHQX2
t
GLQX
t
GHQZ
t
KHQZ
t
ADKH
t
ADSKH
t
DVKH
t
WVKH
t
EVKH
t
KHAX
t
KHADSX
t
KHDX
t
KHWX
t
KHEX
9
—
10
—
11
—
ns
Clock High Pulse Width
4
—
4.5
—
5
—
ns
Clock Low Pulse Width
4
—
4.5
—
5
—
ns
Clock Access Time
—
7.5
—
8
—
8.5
ns
3
Output Enable to Output Valid
—
3.5
—
3.5
—
3.5
ns
3
Clock High to Output Active
0
—
0
—
0
—
ns
3, 4, 5
Clock High to Output Change
2
—
2
—
2
—
ns
4, 5
Output Enable to Output Active
0
—
0
—
0
—
ns
3, 4, 5
Output Disable to Q High-Z
—
3.5
—
3.5
—
3.5
ns
3, 4, 5
Clock High to Q High-Z
2
3.5
2
3.5
2
3.5
ns
3, 4, 5
Setup Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
2.5
—
2.5
—
2.5
—
ns
3
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
0.5
—
0.5
—
0.5
—
ns
3
1.25 V
Output
RL = 50
Zo = 50
Figure 2. AC Test Load
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