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參數(shù)資料
| 型號： | V63C31364097 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128K X 36 CMOS Synchronous Burst Flow-Through SRAM(128Kx36CMOS同步脈沖流經(jīng)過的SRAM) |
| 中文描述： | 128K的米鼠36的CMOS同步突發(fā)流量通過的SRAM（128Kx36CMOS同步脈沖流經(jīng)過的靜態(tài)存儲器） |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 73K |
| 代理商： | V63C31364097 |
MOSEL V ITELIC
V63C31364097
7
V63C31364097 Rev. 0.4 February 1999
Truth Table (See Notes 1 through 5)
Notes
1.
X = Don’t Care. 1 = Iogic high. 0 = Iogic low.
2.
Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3.
G is an asynchronous signal end is not sampled by the clock K. G drives the bus immediately (t
going low
GLQX
) following G
4.
On write cycles that follow read cycles G must be negated prior to the start of the write cycle to ensure proper write
data setup times. G must aIso remain negated at the completion ot the write cycle to ensure proper write data hold
times.
5.
This read assumes the RAM was previously deselected.
Next Cycle
Address
Used
SE1
SE2
SE3
ADSP ADSC
ADV
G
3
DQx
Write 2,4
Deselect
None
1
X
X
X
0
X
X
High-Z
X
Deselect
None
0
X
1
0
X
X
X
High-Z
X
Deselect
None
0
0
X
0
X
X
X
High-Z
X
Deselect
None
X
X
1
1
0
X
X
High-Z
X
Deselect
None
X
0
X
1
0
X
X
High-Z
X
Begin Read
External
0
1
0
0
X
X
X
High-Z
X5
Begin Read
External
0
1
0
1
0
X
X
High-Z
READ
5
Continue Read
Next
X
X
X
1
1
0
1
High-Z
READ
Continue Read
Next
X
X
X
1
1
0
0
DQ
READ
Continue Read
Next
1
X
X
X
1
0
1
High-Z
READ
Continue Read
Next
1
X
X
X
1
0
0
DQ
READ
Suspend Read
Current
X
X
X
1
1
1
1
High-Z
READ
Suspend Read
Current
X
X
X
1
1
1
0
DQ
READ
Suspend Read
Current
1
X
X
X
1
1
1
High-Z
READ
Suspend Read
Current
1
X
X
X
1
1
0
DQ
READ
Begin Write
External
0
1
0
1
0
X
X
High-Z
WRITE
Continue Write
Next
X
X
X
1
1
0
X
High-Z
WRITE
Continue Write
Next
1
X
X
X
1
0
X
High-Z
WRITE
Suspend Write
Current
X
X
X
1
1
1
X
High-Z
WRITE
Suspend Write
Current
1
X
X
X
1
1
X
High-Z
WRITE
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