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參數(shù)資料
| 型號： | V827464K24SXTG-C0 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 214K |
| 代理商： | V827464K24SXTG-C0 |
12
MOSEL VITELIC
V827464K24S
V827464K24S Rev. 1.3 February 2003
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Absolute Maximum Ratings
Note: Operation at above absolute maximum rating can adversely affect device reliability
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
CLK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Write DQS Preamble Setup
Time
tWPRES
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Write DQS Preamble Hold Time tWPREH 0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
CLK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Mode Register Set Delay
tMRD
2
-
2-
2
-
2
-
2
-
CLK
Power Down Exit Time to any
command
tXPDN
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Exit Self Refresh to Non-Read
Command
tXSNR
200
-
200
-
200
-
200
-
75
-
75
-
80
-
CLK
Exit Self Refresh to Read Com-
mand
tXSRD
200
-
200
-
200
-
200
-
200
-
200
-
200
-
CLK
8
Average Periodic Refresh Inter-
val
tREFI
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
us
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD relative to VSS
VDD
-0.5 ~ 3.6
V
Voltage on VDDQ relative to VSS
VDDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
IOS
50
mA
Power Dissipation
PD
9W
Soldering Temperature Time
TSOLDER
260 10
°C Sec
Parameter
Sym-
bol
(DDR400A)
D0
(DDR400B)
D3
(DDR400C)
D4
(DDR333)
C0
(DDR266A)
B1
(DDR266B)
B0
(DDR200)
A1
Unit Note
Min
Max Min
Max Min Max Min Max
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