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參數(shù)資料
| 型號： | VCH16374ADL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs 3-State |
| 中文描述： | LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 7.50 MM, PLASTIC, MO-118AA, SOT-370-1, SSOP3-48 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 82K |
| 代理商： | VCH16374ADL |
Philips Semiconductors
Product specification
74LVC16374A/
74LVCH16374A
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
1998 Mar 17
6
DC ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
°
C to +85
°
C
UNIT
MIN
TYP
1
MAX
I
BHL
Bus hold LOW sustaining current
V
CC
= 3.0V; V
I
= 0.8V
2, 3, 4
V
CC
= 3.0V; V
I
= 2.0V
2, 3, 4
V
CC
= 3.6V
2, 3, 5
V
CC
= 3.6V
2, 3, 5
75
μ
A
I
BHH
Bus hold HIGH sustaining current
–75
μ
A
I
BHLO
Bus hold LOW overdrive current
500
μ
A
I
BHHO
Bus hold HIGH overdrive current
–500
μ
A
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
2. Valid for data inputs of bus hold parts (LVCH16-A) only.
3. For data inputs only, control inputs do not have a bus hold circuit.
4. The specified sustaining current at the data input holds the input below the specified V
I
level.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
6. For bus hold parts, the bus hold circuit is switched off when V
i
exceeds V
CC
allowing 5.5V on the input terminal.
AC CHARACTERISTICS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF; R
L
= 500
; T
amb
= –40
°
C to +85
°
C.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
±
0.3V
TYP
1
V
CC
= 2.7V
V
CC
= 1.2V
UNIT
MIN
MAX
MIN
MAX
MAX
t
PHL
t
PLH
Propagation delay
CP to Qn
1, 4
1.5
3.8
5.4
1.5
6.4
17
ns
t
PZH
t
PZL
3-State output enable time
OE to Qn
2, 4
1.5
3.6
5.6
1.5
6.6
20
ns
t
PHZ
t
PLZ
3-State output disable time
OE to Qn
2, 4
1.5
3.9
5.5
1.5
6.5
12
ns
t
W
CP pulse width
HIGH or LOW
1
3.0
1.5
–
3.0
–
–
ns
t
su
Set-up time Dn to CP
3
2.0
0.3
–
1.9
–
–
ns
t
h
Hold time Dn to CP
3
1.5
–0.3
–
1.1
–
–
ns
f
max
Maximum clock pulse
frequency
1
100
–
–
80
–
–
MHz
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
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