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參數(shù)資料
| 型號(hào)： | VCH16374ADL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs 3-State |
| 中文描述： | LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 7.50 MM, PLASTIC, MO-118AA, SOT-370-1, SSOP3-48 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 82K |
| 代理商： | VCH16374ADL |
Philips Semiconductors
Product specification
74LVC16374A/
74LVCH16374A
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
1998 Mar 17
7
AC WAVEFORMS
V
M
= 1.5V at V
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V; V
X
= V
OL
+ 0.1 V
CC
at V
CC
V
Y
= V
OH
–0.3V at V
CC
2.7V; V
Y
= V
OH
– 0.1 V
CC
at V
CC
2.7V; V
= 0.5 V
at V
2.7V.
2.7V
2.7V
V
M
V
M
1/f
MAX
t
w
t
PHL
t
PLH
CP INPUT
Qn OUTPUT
SW00078
GND
V
OH
V
OL
V
I
Waveform 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency
t
PLZ
t
PZL
V
I
OE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00072
V
M
Waveform 2. 3-State enable and disable times
V
M
SW00079
V
I
GND
éééé
éééé
éééé
V
OH
ééééééé
ééééééé
ééééééé
V
M
Dn
INPUT
V
I
GND
V
M
Qn
OUTPUT
V
OL
CP
INPUT
t
su
t
t
su
t
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Waveform 3. Data set-up and hold times for the Dn input to the
CP input
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
IN
D.U.T.
V
OUT
C
L
V
CC
R
L
=500
SWITCH POSITION
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
SWITCH
Open
2
V
CC
GND
Test Circuit for 3-State Outputs
Open
GND
S
1
2
V
CC
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
R
T
=Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
2.7V
2.7 – 3.6V
V
IN
V
CC
2.7V
SW00047
R
L
=500
Waveform 4. Load circuitry for switching times
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