參數(shù)資料
型號(hào): VE28F008
廠商: Intel Corp.
英文描述: 8 MBIT (1 MBIT x 8) FLASH MEMORY
中文描述: 8兆比特(1兆比特× 8)閃存
文件頁數(shù): 15/26頁
文件大?。?/td> 381K
代理商: VE28F008
VE28F008
Power Supply Decoupling
Flash memory power switching characteristics re-
quire careful device decoupling. System designers
are interested in 3 supply current issues; standby
current levels (I
SB
), active current levels (I
CC
) and
transient peaks produced by falling and rising edges
of CE. Transient current magnitudes depend on the
device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1
m
F ceramic capacitor
connected between each V
CC
and GND, and be-
tween its V
PP
and GND. These high frequency, low
inherent-inductance capacitors should be placed as
close as possible to package leads. Additionally, for
every 8 devices, a 4.7
m
F electrolytic capacitor
should be placed at the array’s power supply con-
nection between V
CC
and GND. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductances.
V
PP
Trace on Printed Circuit Boards
Writing flash memories, while they reside in the tar-
get system, requires that the printed circuit board
designer pay attention to the V
PP
power supply
trace. The V
PP
pin supplies the memory cell current
for writing and erasing. Use similar trace widths and
layout considerations given to the V
CC
power bus.
Adequate V
PP
supply traces and decoupling will de-
crease V
PP
voltage spikes and overshoots.
V
CC
, V
PP
, RP Transitions and the
Command/Status Registers
Byte write and block erase completion are not guar-
anteed if V
PP
drops below V
PPH
. If the V
PP
Status bit
of the Status Register (SR.3) is set to ‘‘1’’, a Clear
Status Register command MUST be issued before
further byte write/block erase attempts are allowed
by the WSM. Otherwise, the Byte Write (SR.4) or
Erase (SR.5) Status bits of the Status Register will
be set to ‘‘1’’s if error is detected. RP transitions to
V
IL
during byte write and block erase also abort the
operations. Data is partially altered in either case,
and the command sequence must be repeated after
normal operation is restored. Device poweroff, or RP
transitions to V
IL
, clear the Status Register to initial
value 10000 for the upper 5 bits.
The Command User Interface latches commands as
issued by system software and is not altered by V
PP
or CE transitions or WSM actions. Its state upon
powerup, after exit from deep powerdown or after
V
CC
transitions below V
LKO
, is Read Array Mode.
After byte write or block erase is complete, even
after V
PP
transitions down to V
PPL
, the Command
User Interface must be reset to Read Array mode via
the Read Array command if access to the memory
array is desired.
Power Up/Down Protection
The VE28F008 is designed to offer protection
against accidental block erasure or byte writing dur-
ing
power
transitions.
VE28F008 is indifferent as to which power supply,
V
PP
or V
CC
, powers up first. Power supply sequenc-
ing is not required. Internal circuitry in the VE28F008
ensures that the Command User Interface is reset to
the Read Array mode on power up.
Upon
power-up,
the
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is
active. Since both WE and CE must be low for a
command write, driving either to V
IH
will inhibit
writes. The Command User Interface architecture
provides an added level of protection since altera-
tion of memory contents only occurs after success-
ful completion of the two-step command sequences.
Finally, the device is disabled until RP is brought to
V
IH
, regardless of the state of its control inputs. This
provides an additional level of memory protection.
Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases us-
able battery life, because the VE28F008 does not
consume any power to retain code or data when the
system is off.
In addition, the VE28F008’s deep powerdown mode
ensures extremely low power dissipation even when
system power is applied. For example, portable PCs
and other power sensitive applications, using an ar-
ray of VE28F008s for solid-state storage, can lower
RP to V
IL
in standby or sleep modes, reducing pow-
er consumption. If access to the VE28F008 is again
needed, the part can again be read, following the
t
PHQV
and t
PHWL
wakeup cycles required after RP is
first raised back to V
IH
. See AC CharacteristicsD
Read-Only and Write Operations and Figures 10 and
11 for more information.
15
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