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參數(shù)資料
| 型號： | VE28F008 |
| 廠商： | Intel Corp. |
| 英文描述： | 8 MBIT (1 MBIT x 8) FLASH MEMORY |
| 中文描述： | 8兆比特（1兆比特× 8）閃存 |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 381K |
| 代理商： | VE28F008 |
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VE28F008
Table 2. Bus Operations
Mode
Notes
RP
CE
OE
WE
A
0
V
PP
DQ
0–7
RY/BY
Read
1, 2, 3
V
IH
V
IL
V
IL
V
IH
X
X
D
OUT
X
Output Disable
3
V
IH
V
IL
V
IH
V
IH
X
X
High Z
X
Standby
3
V
IH
V
IH
X
X
X
X
High Z
X
PowerDown
V
IL
X
X
X
X
X
High Z
V
OH
Intelligent Identifier (Mfr)
V
IH
V
IL
V
IL
V
IH
V
IL
X
89H
V
OH
Intelligent Identifier (Device)
V
IH
V
IL
V
IL
V
IH
V
IH
X
A2H
V
OH
Write
3, 4, 5
V
IH
V
IL
V
IH
V
IL
X
X
D
IN
X
NOTES:
1. Refer to DC Characteristics. When V
PP
e
V
PPL
, memory contents can be read but not written or erased.
2. X can be V
IL
or V
IH
for control pins and addresses, and V
PPL
or V
PPH
for V
PP
. See DC Characteristics for V
PPL
and V
PPH
voltages.
3. RY/BY is V
OL
when the Write State Machine is executing internal block erase or byte write algorithms. It is V
OH
when the
WSM is not busy, in Erase Suspend mode or deep powerdown mode.
4. Command writes involving block erase or byte write are only successfully executed when V
PP
e
V
PPH
.
5. Refer to Table 3 for valid D
IN
during a write operation.
data at the outputs. Chip Enable (CE) is the device
selection control, and when active enables the se-
lected memory device. Output Enable (OE) is the
data input/output (DQ
0
–DQ
7
) direction control, and
when active drives data from the selected memory
onto the I/O bus. RP and WE must also be at V
IH
.
Figure 8 illustrates read bus cycle waveforms.
Output Disable
With OE at a logic-high level (V
IH
), the device out-
puts are disabled. Output pins (DQ
0
–DQ
7
) are
placed in a high-impedance state.
Standby
CE at a logic-high level (V
IH
) places the VE28F008
in standby mode. Standby operation disables much
of the VE28F008’s circuitry and substantially reduc-
es device power consumption. The outputs (DQ
0
–
DQ
7
) are placed in a high-impedence state indepen-
dent of the status of OE. If the VE28F008 is dese-
lected during block erase or byte write, the device
will continue functioning and consuming normal ac-
tive power until the operation completes.
Deep Power-Down
The VE28F008 offers a deep powerdown feature,
entered when RP is at V
IL
. During read modes, RP at
a logic-low level (V
IL
) deselects the memory, places
output drivers in a high-impedence state and turns
off all internal circuits. The VE28F008 requires time
t
PHQV
(see AC Characteristics-Read-Only Opera-
tions) after return from powerdown until initial mem-
ory access outputs are valid. After this wakeup inter-
val, normal operation is restored. The Command
User Interface is reset to Read Array mode, and the
upper 5 bits of the Status Register are cleared to
value 10000, upon return to normal operation.
During block erase or byte write modes, RP at a log-
ic-low level (V
IL
) will abort either operation. Memory
contents of the block being altered are no longer
valid as the data will be partially written or erased.
Time t
PHWL
after RP goes to logic-high (V
IH
) is re-
quired before another command can be written.
Intelligent Identifier Operation
The intelligent identifier operation outputs the manu-
facturer code, 89H; and the device code, A2H for
the VE28F008. The system CPU can then automati-
cally match the device with its proper block erase
and byte write algorithms.
The manufacturer and device codes are read via the
Command User Interface. Following a write of 90H
to the Command User Interface, a read from ad-
dress location 00000H outputs the manufacturer
code (89H). A read from address location 00001H
outputs the device code (A2H). It is not necessary to
have high voltage applied to V
PP
to read the intelli-
gent identifier from the Command User Interface.
7
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