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參數(shù)資料
| 型號： | VG26V17400DJ-6 |
| 英文描述： | DRAM|FAST PAGE|4MX4|CMOS|SOJ|26PIN|PLASTIC |
| 中文描述： | 內(nèi)存|快速頁面| 4MX4 |的CMOS | SOJ | 26PIN |塑料 |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 212K |
| 代理商： | VG26V17400DJ-6 |
Document:1G5-0126
Rev.1
Page 13
VIS
VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Notes :
1. AC measurements assume t
T
= 5ns.
2. An initial pause of 100
is required after power up, and it followed by a minimum of eight initialization
cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is
used, a minimum of eight CAS-before-RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
4. All the V
CC
and V
SS
pins shall be supplied with the same voltage.
5. t
RAS
(min) = t
RWD
(min) + t
RWL
(min) + t
T
in read - modify-write cycle.
6. t
CAS
(min) = t
CWD
(min) + t
CWL
(min) + t
T
in read - modify-write cycle.
7
.
t
ASC
(min), t
RCS
(min), t
WCS
(min) and t
RPC
are determined by the falling edge of CAS.
8. t
RCD
(max) is specified as a reference point only, and t
RAC
(max) can be met with the t
RCD
(max) limit.
Otherwise, t
RAC
is controlled exclusively by t
CAC
if t
RCD
is greater than the specified t
RCD
(max) limit.
9. t
RAD
(max) is specified as a reference point only, and t
RAC
(max) can be met with the t
RAD
(max) limit.
Otherwise, t
RAC
is controlled exclusively by t
AA
if t
RAD
is greater than the specified t
RAD
(max) limit.
10. t
CRP
, t
CHR
, t
RCH
, t
CPA
and t
CPW
are determined by the rising edge of CAS.
11. V
IH
(min) and V
IL
(max) are reference levels for measuring timing or input signals. Therefore, transition
time is measured between V
IH
and V
IL
.
12. Assumes that t
RCD
t
RCD
(max) and t
RAD
t
RAD
(max). If t
RCD
or t
RAD
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown.
13. Assumes that t
RCD
t
RCD
(max) and t
RAD
t
RAD
(max).
14. Access time is determined by the maximum among t
AA
, t
CAC
, t
CPA
.
≤
15. Assumes that t
RCD
t
RCD
(max) and t
RAD
t
RAD
(max).
16. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
17. t
OFF
(max) and t
OEZ
(max) define the time at which the output achieves the open circuit condition (
high impedance).
18. t
WCS
, t
RWD
, t
CWD
, and t
AWD
are not restrictive operating parameters. They are included in the data
≥
sheet as electrical characteristics only. If t
WCS
t
WCS
(min), the cycle is an early write cycle and the
data output will remain open circuit (high impedance) throughout the entire cycle. If t
RWD
≥
≥
t
RWD
(min),
t
CWD
t
CWD
(min), t
AWD
t
AWD
(min), and t
CPW
t
CPW
(min), the cycle is a read-modify-write and the
data output will contain data read from the selected cell. If neither of the above sets of conditions is
satisfied, the condition of the data output (at access time) is indeterminate.
19. These parameters are referenced to CAS in an early write cycle and to WE edge in a delayed write or a
read-modify-write cycle.
20. t
RASP
defines RAS pulse width in Fast page mode cycles.
μ
s
≤
≤
≥
≤
≥
≥
≥
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