參數(shù)資料
型號(hào): VG26V17405EJ-6
英文描述: DRAM|EDO|4MX4|CMOS|SOJ|26PIN|PLASTIC
中文描述: 內(nèi)存| EDO公司| 4MX4 |的CMOS | SOJ | 26PIN |塑料
文件頁(yè)數(shù): 11/27頁(yè)
文件大?。?/td> 214K
代理商: VG26V17405EJ-6
Document:1G5-0124
Rev.1
Page 11
VIS
VG26(V)(S)17405
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Read Cycle
Write Cycle
Read- Modify- Write Cycle
Parameter
Symbol
VG26(V)(S)17405
Unit
Notes
-5
-6
Min
Max
Min
Max
Access time from RAS
t
RAC
-
50
-
60
ns
12
Access time from CAS
t
CAC
-
13
-
15
ns
13, 14
Access time from column address
t
AA
-
25
-
30
ns
14, 15
Access time from OE
t
OEA
-
12
-
15
ns
Read command setup time
t
RCS
0
-
0
-
ns
7
Read command hold time to CAS
t
RCH
0
-
0
-
ns
10, 16
Read command hold time to RAS
t
RRH
10
-
10
-
ns
16
Output buffer turn-off time
t
OFF
0
12
0
15
ns
17
Output buffer turn-off time from OE
t
OEZ
0
12
0
15
ns
17
Parameter
Symbol
VG26(V)(S) 17405
Unit
Notes
-5
-6
Min
Max
Min
Max
Write command setup time
t
WCS
0
-
0
-
ns
7, 18
Write command hold time
t
WCH
8
-
10
-
ns
Write command pulse width
t
WP
8
-
10
-
ns
Write command to RAS lead time
t
RWL
13
-
15
-
ns
Write command to CAS lead time
t
CWL
8
-
10
-
ns
Data-in setup time
t
DS
0
-
0
-
ns
19
Data-in hold time
t
DH
8
-
10
-
ns
19
WE to Data-in delay
t
WED
10
-
10
-
ns
Parameter
Symbol
VG26(V)(S) 17405
Unit
Notes
-5
-6
Min
Max
Min
Max
Read-modify- write cycle time
t
RWC
108
-
133
-
ns
RAS to WE delay time
t
RWD
64
-
77
-
ns
18
CAS to WE dealy time
t
CWD
26
-
32
-
ns
18
Column address to WE delay time
t
AWD
39
-
47
-
ns
18
OE hold time from WE
t
OEH
8
-
10
-
ns
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