參數(shù)資料
型號(hào): VL6524
廠商: 意法半導(dǎo)體
英文描述: VGA single-chip camera module
中文描述: 顯卡單芯片相機(jī)模塊
文件頁(yè)數(shù): 16/70頁(yè)
文件大小: 505K
代理商: VL6524
Clock control
VL6524/VS6524
16/70
5
Clock control
5.1
Input clock
The VL6524/VS6524 contains an internal PLL allowing it to produce accurate frame rates
from a wide range of input clock frequencies. The allowable input range is from 6.5 MHz to
26 MHz. The input clock frequency must be programmed in the uwExtClockFreqNum
(MSB) uwExtClockFreqNum (LSB)and bExtClockFreqDen registers (
Table 12
). To program
an input frequency of 6.5 MHz, the numerator can be set to 13 and the denominator to 2.
The default input frequency is 12 MHz.
5.2
System clock division
It is possible to set an overall system clock division of 2 in the
bEnableGlobalSystemClockDivision register (
Table 12
). This results in a PCLK of 12MHz
and a maximum frame rate of 15fps VGA.
5.3
Pixel clock (PCLK)
All data output from the VL6524/VS6524 is qualified by the PCLK output. The PCLK
frequency is 24 MHz (equivalent to a 12 MHz pixel rate as each pixel is represented by 2
bytes of data). For frame rates less than 30 fps the PCLK frequency is not reduced, instead
additional interframe lines are added into the output data stream.
Figure 4.
Frame output format against framerate
Frame output 30fps
Interframe Blanking
Interframe Blanking
1/30 sec
1/30 sec
1/30 sec
Interframe Blanking
1/15 sec
1/15 sec
Frame output 15fps
Interline
Blanking
Interline
Blanking
ACTIVE VIDEO
ACTIVE VIDEO
Interline
Blanking
ACTIVE VIDEO
Interline
Blanking
ACTIVE VIDEO
Interline
Blanking
ACTIVE VIDEO
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