參數(shù)資料
型號: VL6524
廠商: 意法半導體
英文描述: VGA single-chip camera module
中文描述: 顯卡單芯片相機模塊
文件頁數(shù): 27/70頁
文件大?。?/td> 505K
代理商: VL6524
VL6524/VS6524
Data synchronization methods
27/70
Figure 13.
ITU656 frame structure with even codes
The synchronization codes for odd and even frames are listed in
Table 3
and
Table 4
. By
default all frames output from the VL6524/VS6524 are EVEN. It is possible to set all frames
to be ODD or to alternate between ODD and EVEN using the SyncCodeSetup register in
the
Output formatter control
register bank.
Table 3.
ITU656 embedded synchronization code definition (even frames)
Name
Description
4-byte sequence
SAV
Line start - active
FF 00 00 80
EAV
Line end - active
FF 00 00 9D
SAV (blanking)
Line start - blanking
FF 00 00 AB
EAV (blanking)
Line end - blanking
FF 00 00 B6
EAV
9D
SAV
80
Frame of image data
Line 1
Line 480
Frame blanking period
L
EAV
B6
SAV
AB
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