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| 型號(hào)： | VNC1L-1A |
| 廠商： | Future Technology Devices International Ltd |
| 元件分類： | 總線控制器 |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, GREEN, LQFP-48 |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 672K |
| 代理商： | VNC1L-1A |
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Copyright 2009 Future Technology Devices International Limited
18
Document Reference No.: FT_000030
Vinculum VNC1L Embedded USB Host Controller IC Datasheet Version 2.02
Clearance No.: FTDI# 50
Status Bit
Meaning
0
New Data
Data in current transaction is valid data.
Byte removed from Transmit Buffer.
1
Old Data
This same data has been read in a previous read cycle.
Repeat the read cycle until New Data is received.
Table 5.6 SPI Master Data Read Status Bit
Figure 5.4 SPI Master Data Read (VNC1L Slave Mode)
The status bit is only valid until the next rising edge of SCLK after the last data bit.
During the Data Read operation the CS signal must not be de-asserted.
The transfer completes after 13 clock cycles and the next transfer can begin when SDI and CS are high
during the rising edge of SCLK.
5.2.3 SPI Master Data Transaction
During an SPI master Data Write operation the Start and Setup sequence is sent by the SPI master to
VNC1L, see Figure 5.5. This is followed by the SPI master transmitting each bit of the data to be written
to VNC1L. The VNC1L then responds with a status bit on SDO on the rising edge of the next clock cycle.
The SPI master must read the status bit at the end of each write transaction to determine if the data was
written successfully to VNC1L Receive Buffer. The Data Write status bit is defined in Table 5.7. The status
bit is only valid until the next rising edge of SCLK after the last data bit.
If the status bit indicates Accept then the byte transmitted has been added to VNC1L Receive Buffer. If it
shows Reject then the Receive Buffer is full and the byte of data transmitted in the current transaction
should be re-transmitted by the SPI master to VNC1L.
Any application should poll VNC1L Receive Buffer by retrying the Data Write operation until the data is
accepted.
Status Bit
Meaning
0
Accept
Data from the current transaction was accepted and added to the Receive Buffer
1
Reject
Write data was not accepted.
Retry the same write cycle.
Table 5.7 SPI Master Data Write Status Bit
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|---|---|
| VNC1L-1A-REEL | 功能描述:USB 接口集成電路 USB Vinculum Host /Dev Ctrl IC LQFP-48 RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| VNC1L-1A-TRAY | 功能描述:USB 接口集成電路 USB Vinculum Host /Dev Ctrl IC LQFP-48 RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| VNC2 | 制造商:FTDI 制造商全稱:FTDI 功能描述:VNC2 Debug Module |
| VNC2 DEBUG MODULE | 功能描述:界面開發(fā)工具 USB Vinculum-II Debug/Programmer Mod RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| VNC214B-15A-1D | 制造商:SMC Corporation of America 功能描述:Valve, media, solenoid, body port, 1/2 inch |
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